NXP Semiconductors MPC5606S - Interrupt Flag Register High (IFRH)

FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
694 Freescale Semiconductor
18.3.4.11 Interrupt Flag Register High (IFRH)
This register defines the flags for 32 Message Buffer interrupts. It contains one interrupt flag bit per buffer.
Each successful transmission or reception sets the corresponding IFRH bit. If the corresponding IMRH bit
is set, an interrupt will be generated. The interrupt flag must be cleared by writing a 1 to it. Writing 0 has
no effect.
When the AEN bit in the MCR is set (Abort enabled), while the IFRH bit is set for a MB configured as
Tx, then the writing access done by the CPU into the corresponding MB will be blocked.
18.3.4.12 Interrupt Flag Register Low (IFRL)
This register defines the flags for 32 Message Buffer interrupts and FIFO interrupts. It contains one
interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding IFRL bit. If
the corresponding IMRL bit is set, an interrupt will be generated. The interrupt flag must be cleared by
writing a 1 to it. Writing 0 has no effect.
When the AEN bit in the MCR is set (Abort enabled), while the IFRL bit is set for an MB configured as
Tx, the writing access done by the CPU into the corresponding MB will be blocked.
Table 18-15. IMRL field descriptions
Field Description
BUF31M –
BUF0M
BUF31M–BUF0M — Buffer MB
i
Mask
Each bit enables or disables the respective FlexCAN Message Buffer (MB0 to MB31) interrupt.
0 The corresponding buffer interrupt is disabled
1 The corresponding buffer interrupt is enabled
Note: Setting or clearing a bit in the IMRL register can assert or negate an interrupt request, if the
corresponding IFRL bit is set.
Address: Base + 0x002C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
BUF
63I
BUF
62I
BUF
61I
BUF
60I
BUF
59I
BUF
58I
BUF
57I
BUF
56I
BUF
55I
BUF
54I
BUF
53I
BUF
52I
BUF
51I
BUF
50I
BUF
49I
BUF
48I
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BUF
47I
BUF
46I
BUF
45I
BUF
44I
BUF
43I
BUF
42I
BUF
41I
BUF
40I
BUF
39I
BUF
38I
BUF
37I
BUF
36I
BUF
35I
BUF
34I
BUF
33I
BUF
32I
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-13. Interrupt Flag Register High (IFRH)
Table 18-16. IFRH field descriptions
Field Description
BUF32I –
BUF63I
Buffer MB
i
Interrupt
Each bit flags the respective FlexCAN Message Buffer (MB32 to MB63) interrupt.
0 No such occurrence
1 The corresponding buffer has successfully completed transmission or reception