NXP Semiconductors MPC5606S - Page 857

LIN Controller (LINFlex)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 855
Table 23-19. LINCR2 field descriptions
Field Description
0:16 Reserved
IOBE
17
Idle on Bit Error
0 Bit error does not reset LIN state machine.
1 Bit error reset LIN state machine.
This bit can be set/cleared in Initialization mode only.
IOPE
18
Idle on Identifier Parity Error
0 Identifier Parity error does not reset LIN state machine.
1 Identifier Parity error reset LIN state machine.
This bit can be set/cleared in Initialization mode only.
WURQ
19
Wake-up Generation Request
Setting this bit generates a wakeup pulse. It is reset by hardware when the wakeup character has
been transmitted. The character sent is copied from DATA0 in BDRL buffer. Note that this bit
cannot be set in Sleep mode. Software has to exit Sleep mode before requesting a wakeup. Bit
error is not checked when transmitting the wakeup request.
DDRQ
20
Data Discard Request
Set by software to stop data reception if the frame does not concern the node. This bit is reset by
hardware once LINFlex has moved to idle state. In Slave mode, this bit can be set only when HRF
bit in LINSR is set and identifier did not match any filter.
DTRQ
21
Data Transmission Request
Set by software in Slave mode to request the transmission of the LIN Data field stored in the Buffer
data register. This bit can be set only when HRF bit in LINSR is set.
Cleared by hardware when the request has been completed or aborted or on an error condition.
In Master mode, this bit is set by hardware when DIR bit in BIDR is set and header transmission
is completed.
ABRQ
22
Abort Request
Set by software to abort the current transmission.
Cleared by hardware when the transmission has been aborted. LINFlex aborts the transmission
at the end of the current bit.
This bit can also abort a wakeup request.
It can also be used in UART mode.
HTRQ
23
Header Transmission Request
Set by software to request the transmission of the LIN header.
Cleared by hardware when the request has been completed or aborted.
This bit has no effect in UART mode.
24:31 Reserved