NXP Semiconductors MPC5606S - Page 915

Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 913
Table 25-4. Global Status Register (ME_GS) field descriptions
Field Description
S_CURREN
T_MODE
Current device mode status
0000 Reset
0001 Test
0010 Safe
0011 DRUN
0100 Run0
0101 Run1
0110 Run2
0111 Run3
1000 Halt
1001 Reserved
1010 Stop
1011 Reserved
1100 Reserved
1101 Standby
1110 Reserved
1111 Reserved
S_MTRANS Mode transition status
0 Mode transition process is not active
1 Mode transition is ongoing
S_PDO Output power-down status — This bit specifies output power-down status of I/Os. This bit is asserted whenever
outputs of pads are forced to high impedance state or the pads power sequence driver is switched off.
0 No automatic safe gating of I/Os used and pads power sequence driver is enabled
1 In Safe/Test modes, outputs of pads are forced to high impedance state and pads power sequence driver is
disabled. The inputs are level unchanged. In Stop mode, only pad power sequence driver is disabled but the
state of the output is kept. In Standby mode, the power sequence driver and all pads except those mapped
on wakeup lines are not powered and therefore high impedance. Wakeup lines configuration remains
unchanged
S_MVR Main voltage regulator status
0 Main voltage regulator is not ready
1 Main voltage regulator is ready for use
S_DFLA Data flash availability status
00 Data flash is not available
01 Data flash is in power-down mode
10 Data flash is in low-power mode
11 Data flash is in normal mode and available for use
S_CFLA Code flash availability status
00 Code flash is not available
01 Code flash is in power-down mode
10 Code flash is in low-power mode
11 Code flash is in normal mode and available for use
S_SSCLK1 Secondary system clock source 1 status
0 Secondary system clock source 1 is not stable
1 Secondary system clock source 1 is providing a stable clock
S_FMPLL1 secondary frequency modulated phase locked loop status
0 secondary frequency modulated phase locked loop is not stable
1 secondary frequency modulated phase locked loop is providing a stable clock
S_FMPLL0 primary frequency modulated phase locked loop status
0 primary frequency modulated phase locked loop is not stable
1 primary frequency modulated phase locked loop is providing a stable clock