NXP Semiconductors MPC5606S - Mode Enable Register (ME_ME)

Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 915
NOTE
Byte and half-word write accesses are not allowed for this register as a
predefined key is required to change its value.
25.3.2.3 Mode Enable Register (ME_ME)
Table 25-5. Mode Control Register (ME_MCTL) field descriptions
Field Description
TAR GE T_ M
ODE
Target device mode — These bits provide the target device mode to be entered by software programming. The
mechanism to enter into any mode by software requires the write operation twice: first time with key, and second
time with inverted key. These bits are automatically updated by hardware while entering Safe on hardware
request. Also, while exiting from the Halt and Stop modes on hardware exit events, these are updated with the
appropriate Run0…3 mode value.
0000 Reset
0001 Test
0010 Safe
0011 DRUN
0100 Run0
0101 Run1
0110 Run2
0111 Run3
1000 Halt
1001 Reserved
1010 Stop
1011 Reserved
1100 Reserved
1101 Standby
1110 Reserved
1111 Reserved
KEY Control key — These bits enable write access to this register. Any write access to the register with a value
different from the keys is ignored. Read access will always return inverted key.
KEY: 0101101011110000 (0x5AF0)
INVERTED KEY: 1010010100001111 (0xA50F)
Address 0xC3FD_C008 Access: Supervisor read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0
STANDBY
0 0
STOP
0
HALT
RUN3 RUN2 RUN1
RUN0
DRUN
SAFE
TEST
RESET
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
Figure 25-4. Mode Enable Register (ME_ME)