NXP Semiconductors MPC5606S - Run Peripheral Configuration Registers (ME_RUN_PC0...7)

Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 931
25.3.2.20 Run Peripheral Configuration Registers (ME_RUN_PC0…7)
These registers configure eight different types of peripheral behavior during run modes.
Table 25-12. Peripheral Status Registers 0…3 (ME_PS0…3) field descriptions
Field Description
S_<periph> Peripheral status — These bits specify the current status of the peripherals in the system. If no peripheral is
mapped on a particular position, the corresponding bit is always read as 0.
0 Peripheral is frozen
1 Peripheral is active
Address 0xC3FD_C080–0xC3FD_C09C Access: Supervisor read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0 0
RUN3 RUN2 RUN1 RUN0
DRUN
SAFE
TEST
RESET
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-21. Run Peripheral Configuration Registers (ME_RUN_PC0…7)
Table 25-13. Run Peripheral Configuration Registers (ME_RUN_PC0…7) field descriptions
Field Description
RUN3 Peripheral control during Run3
0 Peripheral is frozen with clock gated
1 Peripheral is active
RUN2 Peripheral control during Run2
0 Peripheral is frozen with clock gated
1 Peripheral is active
RUN1 Peripheral control during Run1
0 Peripheral is frozen with clock gated
1 Peripheral is active
RUN0 Peripheral control during Run0
0 Peripheral is frozen with clock gated
1 Peripheral is active
DRUN Peripheral control during DRUN
0 Peripheral is frozen with clock gated
1 Peripheral is active