NXP Semiconductors
AN11744
PN5180 Evaluation board quick start guide
AN11744 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Application note Rev. 1.3 — 2 February 2018
COMPANY PUBLIC 371213 24 / 45
The test pins can be found at J302 (pin row).
1. Enabling/disabling test bus is stored in the EEPROM
Figure 22. PN5180 analog and digital test signals
The analog test signals can directly be selected, for the digital signals a test bus group
must be chosen first. Two digital test signals can only be selected from one test bus
group at the same time.
4.7 PN5180 Rx Matrix test
The receiver settings of the PN5180 normally need to be optimized to achieve the best
performance. This optimization can be done manually, using the test signals. However,
this manual optimization can be cumbersome, since on one hand some of the register
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