NXP Semiconductors PN544 C2 - Page 127

NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 127 of 172
The proprietary ‘NFCIP1 Target’ gate has the following registry:
Table 120. NFC-IP1 Target Registry
Id Name Access
Rights
Comment Length Default
‘01’ NXP_NFCT_MODE RW
(EE)
Supported NFCIP-1 Modes.
This value shall be interpreted as a bit
mask:
Bit Mode
0 106kbit/s passive
1 212kbit/s passive
2 424kbit/s passive
3 Active
4 ... 7 RFU
0 -> not supported
1 -> supported
1 0x00
‘02’
NXP_NFCT_ATR_REQ
RO
(RAM)
Contains the General Bytes of the
ATR_REQ (max size is 48 bytes)
N N=0
‘03’
NXP_NFCT_ATR_RES
RW
(EE)
Contains the General Bytes of the
ATR_RES (max size is 48 bytes)
N N=0
‘09’
NXP_NFCT_STATUS
RO
(RAM)
Contains the current status of the
NFCIP-1 link when communication has
been set.
0x00 -> data is expected from the host
0x01 -> data is expected from the RF side
Others values are RFU
1 0x00
‘0A’
NXP_NFCT_NFCID3I
RO
(RAM)
Contains the random NFCID3I conveyed
with the ATR_REQ.
10 ‘00000000000000000000’
‘0B’
NXP_NFCT_NFCID3T
RO
(RAM)
Contains the random NFCID3T
conveyed with the ATR_RES.
10 ‘00000000000000000000’