NXP Semiconductors PN544 C2 - Page 170

NXP Semiconductors
UM191812
PN544 C2 User Manual
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in the section 'Legal information'.
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2010-06-16
Document identifier: 191812
14. Contents
1. Introduction .........................................................3
2. PN544 C2..............................................................3
3. Abbreviations ......................................................4
4. References...........................................................6
5. PN544 Software Architecture .............................7
5.1 System Overview ...............................................7
6. Host hardware interface configuration..............8
6.1 General points....................................................8
6.2 SPI interface.....................................................10
6.3 I
2
C interface .....................................................11
6.4 HSU interface...................................................12
7. NXP Logical Link Layer ....................................12
7.1 Overview on physical interfaces.......................13
7.2 Link Layer Features .........................................13
7.3 LLC on SWP ....................................................13
7.4 LLC on I
2
C, SPI, UART ....................................14
7.4.1 Frame definition ...............................................14
7.4.2 Chaining description ........................................15
7.4.3 LLC Header description ...................................17
7.4.3.1 SHDLC frame types .........................................17
7.4.3.2 Control field......................................................17
7.4.3.3 RSET Frame ....................................................19
7.4.3.4 Baud rate change (HSU)..................................21
7.4.4 CRC description ...............................................23
7.4.4.1 Example ...........................................................23
7.4.5 Error Detection and Error Handling ..................24
7.4.5.1 Inter-frame-character timeout...........................24
7.4.5.2 Guard Host Timeout.........................................25
7.4.6 HSU .................................................................26
7.4.6.1 Example: Frame Transfer from Host to PN544 26
7.4.6.2 Example: Frame Transfer from PN544 to Host 26
7.4.6.3 Example: Full Duplex Transfer .........................27
7.4.7 I2C ...................................................................28
7.4.7.1 Example: Communication from Master to Slave
(Host to PN544) ...............................................28
7.4.7.2 Example: Communication from Slave to Master
(PN544 to Host) ...............................................29
7.4.8 SPI ...................................................................30
7.4.8.1 Example: Communication from Master to Slave
(Host to PN544) ...............................................30
7.4.8.2 Communication from Slave to Master (PN544 to
Host) ................................................................31
7.4.8.3 Duplex Communication ....................................32
8. ETSI Host Controller Interface Compliancy ....33
8.1 ETSI HCI Commands/ Events Supported ........33
8.2 ETSI HCI Registries Supported........................36
9. NXP Host Controller Interface ..........................39
9.1 Access Rights NXP HCI Registry .....................39
9.2 Initialization & Default mode of PN544 .............40
9.2.1 Gates & Pipes ..................................................40
9.2.2 Pipe ID allocation .............................................40
9.2.3 First Setup – Initialization phase.......................40
9.2.4 After First Setup – Default state .......................44
9.3 System Management .......................................45
9.3.1 Default mode to Standby mode ........................54
9.3.2 Host Link Wake-up from Standby mode...........55
9.3.3 Information notification .....................................56
9.3.4 Default Secured Element in ‘Power by the Field’
mode ................................................................56
9.3.5 Autonomous mode ...........................................56
9.4 Clock Management ..........................................57
9.4.1 Clock Setup ......................................................57
9.4.1.1 Use of external oscillator ..................................57
9.4.1.2 Use of system clock .........................................58
9.4.2 Supported Clock Request/Acknowledge setup.58
9.4.2.1 Clock Request using GPIO pin.........................59
9.4.2.2 Clock Request using HCI Event .......................60
9.4.3 Clock Request & Release.................................60
9.4.3.1 No clock request...............................................61
9.4.3.2 Request through CLKREQ pin .........................61
9.4.3.3 Request through NXP_EVT_CLK_REQUEST
event ................................................................62
9.4.4 Clock Acknowledge ..........................................63
9.4.4.1 Acknowledge with timeout................................63
9.4.4.2 Acknowledge through CLKACK pin..................64
9.4.4.3 Acknowledge through NXP_EVT_CLK_ACK
event ................................................................65
9.4.5 CLK request in NFC active target mode ...........67
9.5 SWP .................................................................68
9.5.1 Configuration of SWP link.................................71
9.5.1.1 Enabling SWP link............................................71
9.5.1.2 Configuring Request Power pin........................71
9.5.1.3 Changing the baudrate.....................................71
9.5.1.4 Powering the UICC when Vbat < Vbat critical ..71
9.5.1.5 Managing UICC rights in card emulation mode
and in reader mode ..........................................71
9.5.1.6 Reading SWP status ........................................72
9.5.2 Examples of communication with the UICC
connected via SWP ..........................................72
9.5.2.1 Card emulation use case..................................72
9.5.2.2 Reader use case ..............................................74
9.5.3 UICC dependency for PAYPASS Compliance .77