NXP Semiconductors
UM191812
PN544 C2 User Manual
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in the section 'Legal information'.
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2010-06-16
Document identifier: 191812
9.6 Polling Loop .....................................................78
9.6.1 Clock ................................................................81
9.6.2 PollingLoop Management ................................82
9.6.2.1 Detection Guard Time ......................................83
9.6.2.2 Activation Timeout for NFC-IP1 Initiator...........84
9.6.2.3 Activation Timeout for ISO14443-PICC & NFC-
IP1 Target ........................................................84
9.6.2.4 NXP_PL_RDPHASES parameter ....................85
9.6.2.5 NXP_PL_EMULATION, NXP_PL_PAUSE
parameters .......................................................86
9.6.2.6 NXP_EVT_ACTIVATE_RDPHASE,
NXP_EVT_DEACTIVATE_RDPHASE events..90
9.6.3 Example of Polling Loop ..................................92
9.6.4 NFC-IP1 in Polling Loop...................................93
9.6.5 Multi Secure Element .......................................93
9.6.6 RF Configuration ..............................................93
9.6.6.1 Card Emulation RF Step ..................................93
9.6.6.2 Type B, 212kbps and 424kbps Passive Initiator
and Active Initiator/Target ................................94
9.7 NFC-WI ............................................................95
9.8 MIFARE PCD ...................................................99
9.8.1 NXP_MIFARE_RAW........................................99
9.8.2 NXP_MIFARE Commands and Registry........100
9.9 FeliCa Reader ................................................107
9.10 Jewel/Topaz Reader ......................................110
9.11 ISO15693.......................................................113
9.12 NFCIP-1 .........................................................115
9.12.1 Initiator ...........................................................118
9.12.2 Target.............................................................125
9.13 Reader RF gates – additional commands ......129
9.14 Type A PICC ..................................................132
9.14.1 Type A PICC over NFC WI (SMX as a Type A
card)...............................................................132
9.14.2 Type A PICC over SWP (UICC as a Type A
card)...............................................................132
9.14.3 Type A PICC over host link (I2C, SPI, HSU)
(host as a Type A card)..................................132
9.14.4 Multiple Type A PICC.....................................132
9.15 Type A PCD ...................................................133
9.15.1 Type A PCD over SWP (UICC as a Type A
reader) ...........................................................133
9.15.2 Type A PCD over host link (I2C, SPI, HSU) (Host
as a Type A reader) .......................................133
9.15.3 Meaning of additional commands of Reader RF
gates for Type A.............................................133
9.15.3.1 Several Type A cards in the RF field: use
NXP_WR_ACTIVATE_NEXT,
NXP_WR_ACTIVATE_ID...............................133
9.15.3.2 Presence check of ISO14443A card: use
NXP_WR_PRESCHECK................................136
9.15.4 Handling of multiple Type A readers ..............136
9.16 Type B PICC ..................................................139
9.16.1 Type B PICC over SWP (UICC as a Type B
card) ...............................................................139
9.16.2 Type B PICC over host link (I2C, SPI, HSU)
(host as a Type B card) ..................................139
9.16.3 Multiple Type B PICC .....................................139
Type B PCD ....................................................................140
9.16.4 Type B PCD over SWP (UICC as a Type B
reader)............................................................140
9.16.5 Type B PCD over host link (I2C, SPI, HSU) (Host
as a Type B reader)........................................140
9.16.6 Meaning of additional commands of Reader RF
gates for Type B .............................................140
9.16.6.1 Several Type B cards in the RF field: use
NXP_WR_ACTIVATE_NEXT.........................140
9.16.6.2 Presence check of ISO14443B card: use
NXP_WR_PRESCHECK................................140
9.16.7 Handling of multiple Type B readers ..............140
9.17 GPIO(s) ..........................................................141
9.17.1 GPIO Direct Hardware register access...........141
9.17.2 GPIO EEPROM settings access ....................141
9.17.3 Examples........................................................141
9.17.3.1 Output configuration .......................................142
9.17.3.2 Read/write an output pin.................................142
9.17.3.3 Input configuration..........................................143
9.17.3.4 Read an input pin (write is not possible).........143
9.17.3.5 Connect internal Pull up or pull down to the
GPIO ..............................................................143
9.17.3.6 Inverse polarity ...............................................143
9.18 Download .......................................................144
9.18.1 Switch in ‘Download’ mode.............................144
9.19 PN544 Debug Mode.......................................146
9.19.1 SWP digitized .................................................146
9.19.2 PLL Lock & System clock...............................146
9.19.3 RF Level Detector ..........................................147
9.19.4 RF envelope TX .............................................147
9.19.5 RF Signal RX..................................................147
9.20 PN544 Configuration ......................................149
9.20.1 SWP configuration..........................................149
9.20.2 SE configuration .............................................152
9.20.3 HW configuration............................................153
9.20.4 RF configuration .............................................161
9.21 PN544 register access ...................................162
9.21.1 GPIO settings .................................................162
10. Practical Approach on PN544 HCI .................163
10.1 Reading PN544 Version Register...................163
10.2 PN544 Software & Hardware Version ............164
10.3 PN544 Versioning and Configuration
Management ..................................................165
To Next Page
Loading...