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NXP Semiconductors PN7462AU - Pn7462 Au_Ex_Phexccid

NXP Semiconductors PN7462AU
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NXP Semiconductors
UM10883
PN7462 family Quick Start Guide - Development Kit
UM10883
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.614 May 2018
319816
104 of 120
The application APDU commands (L2) are communicated to PN7462AU through SPI
host interface. PN7462AU GPIO pin is used to synchronize command/response between
LPC1769 and PN7462AU.
Interrupt pin is used to notify valid ISO 14443-4 card to LPC1769.
Note
Detailed description and how to use example is described in “POS Use Case Demo
Setup Manual”.
Fig 95. POS demo architecture
9.11 PN7462AU_ex_phExCcid
The PC USB reader application demonstrate how to use the PN7462AU customer demo
board as a CCID reader and shows how connected PN7462AU via USB interface to a
PC and provide the CCID protocol implementation on the top of the physical link.
The PC USB reader example is hosted on the PN7462AU and can be tested with any
PC/SC application running on the PC with Windows OS.

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