PN7462 family Quick Start Guide - Development Kit
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.6 — 14 May 2018
319816
This application requires user interface for performing the operations so it is needed to
use debug mode. Some of the featured system service commands could be irreversible
or reversible depending on the application mode configured by:
#define ENABLE_IR_REVERSIBLE_COMMANDS 0 //1
If the macro ENABLE_IR_REVERSIBLE_COMMANDS is defined to 0, example will not
run irreversible commands, if defined to 1 example will run irreversible commands but
user confirmation is needed.
Table 18. PN7462AU_ex_phSystemServices features
The HW SecRow contains the SWD access bits, code write-
protection bits and RSTN pin behavior bits. For blocking any further
writes to SecRow, the phhalSysSer_OTP_SetSecrowLock() is used.
It prevents further usage of phhalSysSer_OTP_SecrowConfig()
function.
It is required to lock flash memory from write at HW level. It is locked
possibly at a stage when secure secondary upgrade is not planned
for the remaining lifecycle of the product. For such use cases,
phhalSysSer_OTP_SecrowConfig() is used to lock flash memory
from any further write. Any flash programming after locking the flash
results in hard fault. Once SECROW functionality is locked, this
feature cannot be used anymore.
This command disables PN7462AU SWD debug interface. When the
PN7462AU IC is delivered from production to user, the default SWD
access level enables the user to view and debug user flash memory,
user EEPROM memory, user RAM memory, and peripheral registers.
The access level can be irreversibly changed to prevent view/debug
access to any memory region or peripheral registers, before
deploying the IC to the field. phhalSysSer_OTP_SecrowConfig() can
be used to lock the SWD against any further access. Once SECROW
functionality is locked, this feature cannot be used anymore.
Command is used to irreversibly disable the ROM primary download
feature. On subsequent boots, the ROM boot never enters ROM
primary download mode, even if DWL_REQ pin and USB_VBUS pin
is high. This feature is typically used after development and flashing
of secondary downloader in the flash memory, for subsequent
code/data upgrades.
USB Product ID - PID update
USB vendor ID - VID update
Programming
Application asks for FLASH page number. Page is 128bytes long, for
158kb of the flash memory, the page number is in range 0-1263. The
selected flash page is updated from user programmable values.
PVDD is pad voltage reference and supply of the host interface
(HSU, USB, I2C, and SPI) and the GPIOs. This command sets PVDD
configuration to internal.
Commands returns current ROM firmware version
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