NXP Semiconductors PN7462AU - 14 List of Figures

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NXP Semiconductors

UM10883

PN7462 family Quick Start Guide - Development Kit

UM10883

All information provided in this document is subject to legal disclaimers.

User manual

COMPANY PUBLIC

Rev. 1.6 — 14 May 2018

319816

115 of 120

14. List of figures

Fig 1. OM27462CDK Development Kit ....................... 3

Fig 2. OM27462CDKP Development Kit ..................... 4

Fig 3. Properly enumerated USB CCID reader ........... 5

Fig 4. PNEV7462B board ............................................ 6

Fig 5. PNEV7462B supply .......................................... 7

Fig 6. PNEV7462B board schematic (PN7462 part) ... 8

Fig 7. PNEV7462B contact slot interface .................... 9

Fig 8. PNEV7462B TDA8026 part schematics .......... 10

Fig 9. Default 65x65 antenna matching diagram -

symmetrical ..................................................... 12

Fig 10. Matching circuit principle ................................. 12

Fig 11. Antenna and matching .................................... 13

Fig 12. PNEV746B V2.1 ............................................. 14

Fig 13. PNEV7462B V2.2 ........................................... 15

Fig 14. Board Power settings ...................................... 16

Fig 15. VBUS supply jumper setting ........................... 16

Fig 16. Supply indicator .............................................. 17

Fig 17. Default supply connection of the PN7462AU

using all blocks ................................................ 18

Fig 18. Host Interface selection – USB mode ............. 19

Fig 19. Host Interface selection - I2C mode ................ 20

Fig 20. Host Interface selection - SPI .......................... 20

Fig 21. Host Interface selection - HSU ........................ 21

Fig 22. JTAG/SWD debug probe connector ................ 21

Fig 23. PNEV7462C board ......................................... 22

Fig 24. PNEV7462C supply ........................................ 23

Fig 25. PNEV7462C board schematic (PN7462AU

block) .............................................................. 24

Fig 26. PNEV7462C contact slot interface .................. 24

Fig 27. Default 65x65 antenna matching diagram –

symmetrical ..................................................... 26

Fig 28. Matching circuit principle ................................. 26

Fig 29. Antenna and matching .................................... 27

Fig 30. PNEV7462C board power source configuration

........................................................................ 29

Fig 31. PN7462AU VBUS configuration ...................... 29

Fig 32. Power supply status LEDs .............................. 30

Fig 33. Default power supply setting ........................... 31

Fig 34. LPC-Link2 debug probe connected to the

PNEV7462C .................................................... 32

Fig 35. NFC Cockpit: activation of a MIFARE DESFire

EV1 card + Get Application ID ........................ 34

Fig 36. PN7462 NFC cockpit register access ............. 35

Fig 37. PN7462 family IC direct EEPROM access ...... 36

Fig 38. PN7462 family IC analog and digital test signals

........................................................................ 37

Fig 39. PN7462 family IC DPC .................................... 38

Fig 40. PN7462 family IC AWC ................................... 39

Fig 41. Basic Rx Matrix Test set up ............................. 41

Fig 42. Enhanced Rx Matrix Test setup with AWG ..... 42

Fig 43. NI VISA installation ......................................... 44

Fig 44. AWG setup for type A @ 106 .......................... 45

Fig 45. AWG setup for type B @ 106 .......................... 47

Fig 46. Rx Matrix test run example with AWG ............. 48

Fig 47. Rx Matrix Result example with AWG .............. 49

Fig 48. PN7462 family LPCD ...................................... 49

Fig 49. PN7462 family FW tab with EMVCo Loopback

function............................................................ 50

Fig 50. Static overview of PN7462 family firmware ..... 51

Fig 51. Architecture diagram ....................................... 52

Fig 52. Contactless architecture view .......................... 54

Fig 53. Contact architecture view ................................ 55

Fig 54. Project initialization order ................................ 55

Fig 55. FreeRTOS usage diagram .............................. 56

Fig 56. Overview of PN7462AU development

environment .................................................... 57

Fig 57. MCUXpresso installation ................................. 58

Fig 58. Windows security dialog .................................. 59

Fig 59. MCUXpresso IDE ............................................ 59

Fig 60. Importing project to MCUXpresso IDE (1) ....... 60

Fig 61. Importing project to MCUXpresso IDE (2) ....... 61

Fig 62. Select project .................................................. 62

Fig 63. Project Workspace with all examples .............. 63

Fig 64. Building a project ............................................. 64

Fig 65. Build output - flash binary file .......................... 64

Fig 66. Successful build .............................................. 65

Fig 67. Connecting LPC Link2 to the PNEV7462B board

........................................................................ 66

Fig 68. Launch debug session .................................... 67

Fig 69. Selecting debug probe .................................... 67

Fig 70. Project debugging ........................................... 68

Fig 71. Inserting breakpoints ....................................... 69

Fig 72. Debug view and debugger traces .................... 70

Fig 73. Peripheral view ................................................ 71

Fig 74. PN7462AU EECTRL peripheral view .............. 72

Fig 75. HW setup for the flashing via LPC-Link 2 ........ 73

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