NXP Semiconductors PXN2020 - 8.3.2.3 System Reset Control Register (SIU_SRCR)

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 8-15
8.3.2.3 System Reset Control Register (SIU_SRCR)
Table 8-5. SIU_RSR Field Descriptions
Field Description
PORS Power-on Reset Status. Set for any power-on or LVI reset. Also set on recovery from sleep mode.
0 The reset controller acknowledged another reset source since the last assertion of the power-on reset input.
1 The power-on reset input to the reset controller is asserted, and no other reset source has been acknowledged
since that assertion of the power-on reset input except an external reset.
ERS External Reset Status. (Asynchronous reset source)
0 Last reset source the reset controller acknowledged was not a valid assertion of the RESET
pin.
1 Last reset source the reset controller acknowledged was a valid assertion of the RESET
pin.
LLRS Loss-of-Lock Reset Status. (Asynchronous reset source)
0 Last reset source the reset controller acknowledged was not a loss of PLL lock reset.
1 Last reset source the reset controller acknowledged was a loss of PLL lock reset.
LCRS Loss-of-Clock Reset Status. (Asynchronous reset source)
0 Last reset source the reset controller acknowledged was not a loss of clock reset.
1 Last reset source the reset controller acknowledged was a loss of clock reset.
WDRS Watchdog Timer Reset Status.
0 Last reset source the reset controller acknowledged was not a watchdog timer reset.
1 Last reset source the reset controller acknowledged was a watchdog timer reset.
CRS Checkstop Reset Status. Set for Z6 or Z0 core reset.
0 Last reset source the reset controller acknowledged was not an enabled checkstop reset.
1 Last reset source the reset controller acknowledged was an enabled checkstop reset.
SSRS Software System Reset Status.
0 Last reset source the reset controller acknowledged was not a software system reset.
1 Last reset source the reset controller acknowledged was a software system reset.
BOOTCFG Status of BOOTCFG pin at negation of RESET.
Offset: SIU_BASE + 0x0010 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
SSR
1
000
RSVD
00000000000
W
Reset0 000 1 000 00000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CRE1 CRE0
000000
SSRL
3
000
RSVD
000
W
Reset 1
2
1
2
00 0 000 00000000
1
The SSR bit always reads as zero. A write of zero to this bit has no effect.
2
The CRE0/1 bits are reset to 0b1 by POR. Other resets sources do not reset the bit value.
3
Once written to a 1, the SSRL bit can be reset only to zero by POR.
Figure 8-4. System Reset Control Register (SIU_SRCR)