NXP Semiconductors PXN2020 - 8.3.2.4 External Interrupt Status Register (SIU_EISR)

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-16 Freescale Semiconductor
8.3.2.4 External Interrupt Status Register (SIU_EISR)
The external interrupt status register is used to record edge-triggered events on the IRQ0–IRQ15 and
NMI0–NMI1 inputs to the SIU. When an edge-triggered event is enabled in the SIU_IREER or
SIU_IFEER for an IRQn input and then sensed, the corresponding SIU_EISR flag bit is set. The IRQ flag
bit is set, regardless of the state of the corresponding DMA/IRQ enable bit in SIU_DIRER (SIU_DIRER
only affects interrupts and has no effect on enabling/selecting DMA requests). The IRQ flag bit remains
set until cleared by software or through the servicing of a DMA request. The IRQ flag bits are cleared by
writing a 1 to the bits. A write of 0 has no effect.
Table 8-6. SIU_SRCR Field Descriptions
Field Description
SSR Software System Reset. Used to generate a software system reset. Writing a 1 to this bit causes an internal reset.
The software system reset is processed as a synchronous reset. The bit is automatically cleared on the assertion
of any other reset source except a software external reset.
0 Do not generate a software system reset.
1 Generate a software system reset.
RSVD Reserved for system use. Do not write to this bit.
CRE1 Checkstop Reset Enable (enable secondary CPU, Z0, checkstop to generate reset). Writing a 1 to this bit enables
a reset when the e200z0 checkstop reset request input is asserted. The checkstop reset request input is a
synchronous internal reset source. The CRE1 bit defaults to checkstop reset enabled at POR. If this bit is cleared,
it remains cleared until the next POR.
0 No reset occurs when the e200z0 checkstop reset input to the reset controller is asserted.
1 A reset occurs when the e200z0 checkstop reset input to the reset controller is asserted.
CRE0 Checkstop Reset Enable (enable primary CPU, Z6, checkstop to generate reset). Writing a 1 to this bit enables a
reset when the e200z6 checkstop reset request input is asserted. The checkstop reset request input is a
synchronous internal reset source. The CRE0 bit defaults to checkstop reset enabled at POR. If this bit is cleared,
it remains cleared until the next POR.
0 No reset occurs when the e200z6 checkstop reset input to the reset controller is asserted.
1 A reset occurs when the e200z6 checkstop reset input to the reset controller is asserted.
SSRL Software System Reset Lock. This bit is used to disable the software system reset. This bit defaults to 0. A write of
1 disables the SSR bit until the next POR (write once).
0 Enable the SSR bit.
1 Disable the SSR bit.
RSVD Reserved for system use. Do not write to this bit.
Note: Once written to a 1, this bit can be reset to 0 only by POR. When this bit is set, bit 4 is automatically cleared.