NXP Semiconductors PXN2020 - 8.3.2.25 eMIOS Select Register n (SIU_EMIOS_SELn)

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-44 Freescale Semiconductor
8.3.2.25 eMIOS Select Register n (SIU_EMIOS_SELn)
The SIU_EMIOS_SELn register specifies the source for the eMIOS[31:0] input channels, thus allowing
the timer input channels to come from the pins, or from the deserialized output of one of the four DSPI
modules. Each 4-bit field (32 fields across the four SIU_EMIOS_SELn registers) in this set of registers
individually controls the setting for one eMIOS input channel.
Offset: SIU_BASE + 0x09B4 Access: User read/write
0123456789101112131415
R
EMIOSSEL31 EMIOSSEL30 EMIOSSEL29 EMIOSSEL28
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EMIOSSEL27 EMIOSSEL26 EMIOSSEL25 EMIOSSEL24
W
Reset0000000000000000
Figure 8-30. eMIOS Select Register 0 (SIU_EMIOS_SEL0)
Offset: SIU_BASE + 0x09B8 Access: User read/write
0123456789101112131415
R
EMIOSSEL23 EMIOSSEL22 EMIOSSEL21 EMIOSSEL20
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EMIOSSEL19 EMIOSSEL18 EMIOSSEL17 EMIOSSEL16
W
Reset0000000000000000
Figure 8-31. eMIOS Select Register 1 (SIU_EMIOS_SEL1)
Offset: SIU_BASE + 0x09BC Access: User read/write
0123456789101112131415
R
EMIOSSEL15 EMIOSSEL14 EMIOSSEL13 EMIOSSEL12
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EMIOSSEL11 EMIOSSEL10 EMIOSSEL9 EMIOSSEL8
W
Reset0000000000000000
Figure 8-32. eMIOS Select Register 2 (SIU_EMIOS_SEL2)