e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 13-21
13.3.1.5.6 MAS[6] Register
The MAS[6] register is shown in Figure 13-12.
MAS[6] fields are defined in Table 13-9.
13.3.2 L1 Cache
The e200z6 processor supports a 32 KB, 4- or 8-way set-associative, unified (instruction and data) cache
with a 32-byte line size. The cache improves system performance by providing low-latency data to the
e200z6 instruction and data pipelines, which decouples processor performance from system memory
performance. The cache is virtually indexed and physically tagged. The e200z6 does not provide hardware
support for cache coherency in a multi-master environment. Software must be used to maintain cache
coherency with other possible bus masters.
Both instruction and data accesses are performed using a single bus connected to the cache. Addresses
from the processor to the cache are virtual addresses used to index the cache array. The MMU provides the
virtual to physical translation for use in performing the cache tag compare. If the physical address matches
a valid cache tag entry, the access hits in the cache. For a read operation, the cache supplies the data to the
processor, and for a write operation, the data from the processor updates the cache. If the access does not
Table 13-8. MAS[4]—Hardware Replacement Assist Configuration Register
Field Description
TLBSELD Default TLB selected
01 TLB1 (ignored by the e200z6, write as 01 for future compatibility)
TIDSELD Default PID# to load TID from
00 PID0
01 Reserved, do not use
10 Reserved, do not use
11 TIDZ (0x00)) (Use all zeros, the globally shared value)
TSIZED Default TSIZE value
VLED Default VLED value
DWIMGE Default WIMGE values
SPR: 630 Access: Read/write
0123456789101112131415161718192021222324252627282930 31
R
—SPID — SAS
W
Reset Undefined on Power Up Unchanged on Reset
Figure 13-12. MMU Assist Register 6—MAS[6]
Table 13-9. MAS[6]—TLB Search Context Register 0
Field Description
SPID PID value for searches
SAS AS value for searches
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