NXP Semiconductors PXN2020 - 14.2.1 Instruction Unit Features

e200z0 Core (Z0)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 14-3
dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use
dependency does not incur any pipeline bubbles for most cases.
The Condition Register unit supports the condition register (CR) and condition register operations defined
by the Power Architecture. The condition register consists of eight 4-bit fields that reflect the results of
certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions,
and provide a mechanism for testing and branching.
Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to
allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead.
Figure 14-1. e200z0 Block Diagram
14.2.1 Instruction Unit Features
The features of the e200 Instruction unit are:
• 32-bit instruction fetch path supports fetching of one 32-bit instruction per clock, or as many as
two 16-bit VLE instructions per clock.
• Instruction buffer with two entries, each holding a single 32-bit instruction, or a pair of 16-bit
instructions
CPU
control logic
Load/
store
unit
Instruction Unit
Branch
unit
PC
unit
Instruction Buffer
GPR
CR
SPR
Multiply
unit
OnCE/Nexus
control logic
interface
Control
Data
(mtspr/mfspr)
Integer
execution
unit
External
SPR
CTR
XER
LR
DataAddress
Instruction bus interface unit
Control
32
64 N