NXP Semiconductors PXN2020 - 20.3.2.5 SWT Service Register (SWT_SR); 20.3.2.6 SWT Counter Output Register (SWT_CO)

Software Watchdog Timer (SWT)
PXN20 Microcontroller Reference Manual, Rev. 1
20-6 Freescale Semiconductor
20.3.2.5 SWT Service Register (SWT_SR)
The SWT Time-Out (SWT_SR) service register is the target for service operation writes used to reset the
watchdog timer.
20.3.2.6 SWT Counter Output Register (SWT_CO)
The SWT Counter Output (SWT_CO) register is a read-only register that shows the value of the internal
down counter when the SWT is disabled.
Offset: SWT_BASE + 0x0010 Access: User read/write
0123456789101112131415
R 0 0 0 0 0 00000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 00000000000 0 00
WWSC
Reset0000000000000000
Figure 20-5. SWT Service Register (SWT_SR)
Table 20-6. SWT_SR Field Descriptions
Field Description
WSC Watchdog Service Code.This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If
the SWT_CR[KEY] bit is set, two pseudorandom key values are written to service the watchdog, see Section
Section 20.4, Functional Description, for details. Otherwise, the sequence 0xA602 followed by 0xB480 is written to
the WSC field. To clear the soft lock bit (SWT_CR[SLK]), the value 0xC520 followed by 0xD928 is written to the WSC
field.
Offset: SWT_BASE + 0x0014 Access: User read-only
0123456789101112131415
R CNT
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CNT
W
Reset0000000000000000
Figure 20-6. SWT Counter Output Register (SWT_CO)