DMA Channel Multiplexer (DMA_MUX)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 23-9
Figure 23-3. DMA_MUX Channel 0–7 Block Diagram
The DMA channel triggering capability allows the system to schedule regular DMA transfers, usually on
the transmit side of certain peripherals, without the intervention of the processor. This trigger works by
gating the request from the peripheral to the DMA until a trigger event has been seen. This is illustrated in
Figure 23-4.
Figure 23-4. DMA_MUX Channel Triggering: Normal Operation
After the DMA request has been serviced, the peripheral negates its request, effectively resetting the gating
mechanism until the peripheral re-asserts its request AND the next trigger event is seen. This means that
if a trigger is seen, but the peripheral is not requesting a transfer, that triggered is ignored. This situation
is illustrated in Figure 23-5.
Peripheral Source #1
Peripheral Source #2
Peripheral Source #3
Peripheral Source #55
DMA Channel #n
Always Disabled
Always Enabled
CHCONFIGn[SOURCE]
PIT Trigger #n+1
1
0
CHCONFIGn[TRIG]
Source #60
Always Enabled
Source #63
n = 0 to 7
Source #0
Peripheral Request
Trigger
DMA Request
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