Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-24 Freescale Semiconductor
Figure 28-16. Single Action Input Capture with Both Edges Triggering Example
28.4.1.1.3 Single Action Output Compare (SAOC) Mode
In SAOC mode (MODE = 000_0011), a match value is loaded in register A2 and then transferred to
register A1 to be compared with the selected time base. When a match occurs, the EDSEL bit selects if the
output flip-flop is toggled or if the value in EDPOL is transferred to it. At the same time, the FLAG bit is
set to indicate that the output compare match has occurred. Writing to register EMIOS_CADR[n] stores
the value in register A2 and reading to register EMIOS_CADR[n] returns the value of register A1.
An output compare match can be simulated in software by setting the FORCMA bit in EMIOS_CCR[n]
register. In this case, the FLAG bit is not set.
When SAOC mode is entered coming out from GPIO mode the output flip-flop is set to the complement
of the EDPOL bit in the EMIOS_CCR[n] register.
Counter bus can be either internal or external and is selected through the BSL bits.
Figure 28-17 and Figure 28-18 show how the unified channel can be used to perform a single output
compare with EDPOL value being transferred to the output flip-flop and toggling the output flip-flop at
each match, respectively.
Figure 28-17. SAOC Example—EDPOL Value Being Transferred to the Output Flip-flop
Selected Counter Bus
0x001000 0x001102
FLAG Set Event
A2 (Captured) Value
2
0xxxxxx 0x001000
Input Signal
1
Edge detect
0x001103 0x0011080x001104 0x001105 0x001106 0x001107
0x001001
FLAG Pin/Register
Edge detect
FLAG Clear
Edge detect
0x001103 0x001108
EDSEL = 1
EDPOL = x
Notes:
1
2
After input filter
EMIOS_CADR[n] A2
Selected
Counter Bus
FLAG
Set Event
A1 Match A1 Match A1 Match
0xxxxxxx 0x001000 0x001000 0x001000
Notes:
1
0x000500 0x001000 0x001100 0x001000 0x001100 0x001000
EMIOS_CADR[n] = A2
A2 = A1 according to OU[n] bit
Update to
A1
EDSEL = 0
Output
Flip-Flop
EDPOL = 1
A1 Value
1
0x001000
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