NXP Semiconductors PXN2020 - 30.4.5.2 CSI Deserialization

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-39
Figure 30-24. CSI Serialization Diagram
The parallel inputs signal states are latched into the DSPI DSI Serialization Data Register (DSPI_SDR) on
the rising edge of every system clock and serialized based on the transfer initiation control settings in the
DSPI_DSICR. For more information on the DSPI_SDR, refer to Section 30.3.2.11, DSPI DSI
Serialization Data Register (DSPI_SDR). SPI frames written to the TX FIFO have priority over DSI data
from the DSPI_SDR and are transferred at the next frame boundary. A copy of the most recently
transferred DSI frame is stored in the DSPI_COMPR. The transfer priority logic selects the source of the
serialized data and asserts the appropriate chip select signal.
30.4.5.2 CSI Deserialization
The deserialized frames in CSI configuration go into the DSPI_SDR or the RX FIFO based on the transfer
priority logic. When DSI frames are transferred, the returned frames are deserialized and latched into the
DSPI_DDR. When SPI frames are transferred, the returned frames are deserialized and written to the RX
FIFO. Figure 30-25 shows the CSI deserialization logic.
Figure 30-25. CSI Deserialization Diagram
SOUTx
Parallel
DSI control
register
DSI transmit
comparison register
Clock
logic
0 1 • • • • • 15
Shift register
DSI serialization
data register
Control
logic
SCKx
inputs
PCSx (SPI)
PCSy (DSI)
16
16
16
16
Transfer
Slave bus interface
16
TX FIFO
(P_IN)
priority logic
SIN
Control
logic
0 1 • • • • • 15
Shift register
16
Slave bus interface
Parallel
DSI deserialization
data register
outputs
16
Transfer
priority logic
16
RX FIFO
(P_OUT)
16