NXP Semiconductors QorIQ LS1043ARDB - Page 15

J4
Up: UART2
Down: UART1
SW1
Reset
switch
P1
Up: RGMII2
Down: RGMII1
J3
10G port
P3
Up: QSGMII.P1
Down: QSGMII.P0
J2
Up: USB2
Down: USB1
J1
+12 V power jack
SW2
Power switch
P2
Up: QSGMII.P3
Down: QSGMII.P2
J8
CPLD JTAG
P4
PCIe slot
P5
Mini-PCIe slot
J11
TDM slot
J17
Chassis fan
J16
CPU JTAG
J18
K22 JTAG
J20
Mini-USB to UART1
BT1
RTC battery
Figure 1-3. LS1043ARDB top view
The figure below shows the LS1043ARDB bottom view.
Chapter 1 Introduction
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
NXP Semiconductors 15