LS1043A
DDR4
(MT40A512M8)
DDR4_A[0:14], BA[0:2]
MRAS_B, MCAS_B, MWE_B
MCK, MCK_B, MCKE[0:1], MODT[0:1]
MCS[0:1]_B
MDQ[0:31]
MDQS[0:3], MDQS[0:3]_B
MDM[0:3]
Figure 2-1. DDR memory architecture
For power supply details for the DDR interface, see DDR supply.
2.2
IFC interface
The LS1043ARDB integrated flash controller (IFC) has the following features:
• Supports 1.8 V I/O voltage
• Implements little endian support
• Supports 28-bit addressing and 16-bit data bus
• Supports GPCM, NOR, and NAND FCM
• Supports the following IFC clients on the LS1043ARDB:
• NAND flash (async/sync - ONFI 1.0 compatible)
• NOR flash 16-bit
The figure below shows the IFC block diagram.
IFC interface
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
18 NXP Semiconductors
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