CPLD
LS1043A
JTAG header
Push
button
MAX
811
CPLD_TRST_B_18
RST_PLD_B
K22
MCU
RST_TGTMCU
JTAG_RST_B_18
CPU_TRST_B_18
PORESET_B_18
HRESET_B_18
RESET_REQ_B_18
RST_PCIE_N
mPCIe and PCIe
slot
TDM
slot
DDR4
#1-4
NOR flash
RGMII1&2
RTL8211
QSGMII
F104S8
XGT PHY
ARQ105
TDMR_RST_N
XGT_RST_B
DDR_RST_B
ETHPHY_RST_B
QSGMII_RST_B
RST_FLSH_B
Figure 3-4. Reset architecture
3.5
DDR supply
The LS1043ARDB DDR power supply provides to the DDR4 interface the voltages
shown in the table below.
Table 3-4. DDR supply voltages
Voltage name Voltage Current Description
GVDD 1.2 V <= 2.5 A DRAM core and I/O voltage
DDR_VREFCA 0.6 V >= 10 mA DRAM reference voltage
DDR_VTT 0.6 V <= 1 A Bus termination supply
+2V5_VPP 2.5 V < 200 mA DRAM activating power supply
The LS1043ARDB uses the VR500 (U33) switching power controller as follows:
Chapter 3 Power Supplies and CPLD Controller
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
NXP Semiconductors 41
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