NXP Semiconductors QorIQ T1040 - 2.3 Clocks

BEAD
ATX PS
12V_SLP
5V0_SLP
VCORE_EN
VCORE_PGOOD
CPLD
PM_BUS
VPG
R
egulator
IR36021/
3550
3V3_SLP
VCC_DRV_3.3V
VCC_DRV_7V
12V_SLP
MIC30102
YM
SVO_SLP
IOPWR_EN
1V0 (4A)
1V5 (1.5A)
IR3473
1V35
1V8
2V5
3V3
VTT/MVREF
1V0S
DVDD
MIC47100
TPS51200
1V35_SLP
1V8_SLP
VDD_EN
2V5
EVDD_SEL
For T1040,DVDD=3.3V
3V3
EVDD
3V3
1V8
T2081_EN
12V_SLP
OPWR_EN
3V3
12V
1V0_LP
NCP571
12V
BATH/BATL
DC/DC
3V3
OVDD_SLP
3V3_SLP
1V8_SLP
EPM570
VDD
PCA9546
BATH/BATL
3V3
5V0_SLP
USB:MIC2506
DVDD/AVDD
Le88266*2
SD Card
IN
VDD
3V3
SPI FLASH
N25QS1
2A13G
VCC
3V3
3V3
NAND FLASH
MT29F8G08ABB
AWP
VCC/VCOD
VIO
OVDD
3V3
VCC
NOR FLASH
JS28F00AM29EWHA
2V5
VDD25/VDD25A
VSC8514*2
VDD1/VDD1A
1V0
OVDD_SLP
VCCRE
J11
IDT9FGV0641
ICS843002*2
3V3
1V8_SLP
OVDD
OVDD_SLP
100M OSC
S
ys_refclk
66.67M OSC
DDR_r
efclk
VCORE_SLP_40A
VCORE
VDD_EN
VCORE_EN
CPLD
1V35
OVDD_SLP
0.33ohm
OVDD
VCORE_SLP
3V3_SLP
OVDD_SLP
1V05
1V35
1V8_SLP
3V3_SLP
1V8
3V3
0ohm[NC]
MVREF
1V0_LP
OVDD
OVDD
OVDD_SLP
0ohm[NC]
0ohm
BEAD
XVDD
AVDD_SD1_PLL1
AVDD_SD1_PLL2
AVDD_PLAT
AVDD_D1
AVDD_CGA1
AVDD_CGA2
USB_SVDD[1:2]
USB_HVDD[1:2]
USB_OVDD[1:2]
S1VDD[1:7]
X1VDD[1:5]
T1040
O1VDD[1:3]
OVDD[1:8]
D1_MVREF
VDD_IP
TH_VDD
FA_VL
PROG_MTR
PROG_SFP
EVDD1
DVDD[1:3]
CVDD1
LVDD[1:2]
L1VDD[1:2]
G1VDD[1:19]
VDD[1:47]
VDDC[1:7]
PIPCIE3212*5
VDD
3V3
3V3
3V3_SLP
VDD
MAX3232*2
AVDD/DVDO
RTL8211E-VB
U49
DVDD(15/21)
2V5_SLP
3V3
AVDD/DVDD
RTL8211E-VB/DN
U46/U52
DVDD(15/21)
2V5
3V3
12V
3V3
12V
TDM SLOT
PCIEX4 SLOT
1V5
3V3
MINI PCIE SLOT*2
12V
FAN Conn *4
SVO_SLP
IOPWR_EN
IR3473
IR3473
SVO_SLP
IR3473
SVO_SLP
IR3473
SVO_SLP
IR3473
SVO_SLP
OPWR_EN
(Always_On)
3V3_SLP(9A)
OPWR_EN
(Always_On)
2V5_SLP(1.5A)
ODRPWR_EN
(Always_On)
1V35_SLP(6.5A)
(Switchable)
(Switchable)
VDD_EN
IOPWR_EN
DDRPWR_EN
EVDD_SEL
T2081_EN
OPWR_EN
(Always_On)
1V8_SLP(2A)
SVDD
0ohm
BEAD
BEAD
BEAD
0.33ohm
5.1ohm
5.1ohm
5.1ohm
5.1ohm
J10
J9
EVDD
DVDD
OVDD
2V5
2V5_SLP
1V5_SLP
VCORE
VCORE_SLP
Figure 2-1. Power distribution
2.3 Clocks
The clock circuitry provides clocks for the processor for:
•
SYSCLK (single-ended and differential)
• DDRCLK
• SerDes clocks (two independent options)
Chapter 2 Architecture
QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015
Freescale Semiconductor, Inc. 15