NXP Semiconductors QorIQ T1040 - Page 21

T1040
SD1_RXn/TXn_P/N
PI3PCIE321
2
SGMII_RX/TX
RTL8211DN
(SGMII_PHY)
F104S8A
(QSGMII_PHY)
SD1_RXn/TXn_P/N(QSGMII2_RX/TX)
CPLD
SD1_RXn/TXn_P/N(PEX[0])
MPEX[1]
PEX[1]
Mini_PCle
SLOT
SATA
SD1_RXn/TXn_P/N
SD1_RXn/TXn_P/N
SD1_RXn/TXn_P/N
SD1_RXn/TXn_P/N
PI3PCIE3212
PI3PCIE3212
PI3PCIE3212
PI3PCIE3212
QSGMII1_RX/TX
MPEX[2]
PEX[2]
PEX[3]
SATA
Mini_PCle
SLOT
PCle SLOT
F104S8A
(QSGMII_PHY)
n - [0:7]
SD1_RXn/TXn_P/N
Figure 2-5. SerDes lane connections
Chapter 2 Architecture
QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015
Freescale Semiconductor, Inc. 21