Table 2-12. POR configuration through switches
(continued)
SW2[5:6] cfg_svr[0:1] IFC_A[16:17] Reserved Reserved
SW2[7] cfg_dram_type IFC_A21 DRAM type selection 0: DDR4(1.2V)
1: DDR3L(1.35V)
SW2[8] cfg_rsp_dis IFC_AVD Reserved Reserved
SW3[1] cfg_eng_use0 IFC_WE0 Sys_clock selection 0: differential sys_clk is
selected
1:single sys_clk is
selected
SW3[2:3] cfg_eng_use[1:2] Reserved Reserved Reserved
SW3[4] BOOT_FLASH_SEL - Boot flash selection 0: NOR Flash
1: NAND Flash
1
SW3[5:7] CFG_VBANK[0:2] - Flash bank select 0: Default
2
SW3[8] TEST_SEL_N TEST_SEL_B - 0: T1020
1: T1040
1. For SW3[4] : BOOT_FLASH_SEL, it can act as boot flash selection. When BOOT_FLASH_SEL=0, NOR Flash is boot
flash, when BOOT_FLASH_SEL=1, NAND Flash is boot flash.
2. SW3[5:7] can be used to change the staring address for the memory banks. For example, the NOR FLASH memory is
divided into eight memory banks with 16MB size each. Eight different U-Boot image can be programmed into each
memory bank, though normally only settings for bank 0 and bank 4 are used. When NOR FLASH is selected as boot flash
(CS0 is connected to NOR FLASH by setting SW3[4] to ON, RCW[0:8] is set to 0_0111_xxxx using SW1[1:8] and SW2[1]),
a different U-Boot image can be selected to boot up the board, by setting SW3[5:7].
For other boot sources configured by the DIP switch, see the QorIQ T1040 Reference Manual (T1040RM).
DIP switch definition
QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015
40 Freescale Semiconductor, Inc.
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