8. Click Start. The 100% status on the progress bar indicates that the CPLD is
programmed successfully.
3.2 CPLD memory map
memory map
Offset
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
0 Chip ID1 register (CHIPID1) 8 R 55h 3.2.1/44
1 Chip ID2 register (CHIPID2) 8 R AAh 3.2.2/45
2 Hardware version register (HWVER) 8 R See section 3.2.3/45
3 Software version register (SWVER) 8 R See section 3.2.4/46
10 Reset control register (RSTCON1) 8 w1c See section 3.2.5/46
11 Reset control register (RSTCON2) 8 w1c See section 3.2.6/47
12 INTSR 8 R See section 3.2.7/48
13 Flash control and status register (FLHCSR) 8 R/W See section 3.2.8/49
14 Fan control and status register (FANCSR) 8 R/W 3.2.9/49
15 Panel LED control and status register (LEDCSR) 8 R/W See section 3.2.10/50
16 SFP+ control and status register (SFPCSR) 8 R/W 00h 3.2.11/51
17 Miscellaneous control and status register (MISCCSR) 8 R/W See section 3.2.12/51
18 Boot configuration override register (BOOTOR) 8 R/W See section 3.2.13/52
19 Boot configuration register 1 (BOOTCFG1) 8 R/W See section 3.2.14/52
1A Boot configuration register 2 (BOOTCFG2) 8 R/W See section 3.2.15/52
CPLD memory map
QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015
44 Freescale Semiconductor, Inc.
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