NXP Semiconductors S32K3X4EVB-Q172 - LIN Interface

NXP Semiconductors
S32K3X4EVB-Q172 HWUM
S32K3X4EVB-Q172 | S32K3X4EVB-S172 - Hardware User Manual
S32K344EVB-Q172 | -S172 HWUM
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NXP Semiconductors
REV A – 10/2021
Page 17 of 31
Table 9. Programming and Debug Connectors
9 S32K3X4EVB-Q172 | -S172 - LIN Interface
The EVB incorporates two LIN interfaces connected the S32K344 MCU. Using an NXP LIN transceivers the
TJA1021T/20/C, supporting both master and slave mode (jumper selectable). The output from the LIN transceivers is
connected to J23.
Figure 14. S32K3X4EVB-Q172 | -S172 – LIN Interface
Connector
Reference/
Component
Description
20-Pin Cortex
Debug + ETM
Connector
J50
This small 20-pin (0.05") connector provides access to SWD, SWV, JTAG, and ETM
(4-bit) signals available on a Cortex-M3/M4/M7 device.
A 20-pin header (Samtec FTSH-110-01) is specified with dimensions:
0.50" x 0.188" (12.70 mm x 4.78 mm).
NOTE - JTAG – TRACE Signals
Due that the MCU ports used for the trace signals also are shared with other
interfaces. It is important to isolate these signals/interfaces for the J4-Cortex Debug
D ETM connector.
SIGNAL
Name
MCU
Port
Name
Signal
Resistor
COMMENT
TRACE_CLK
PTC2
R
Disabled as DEFAULT
TRACE_D0
PTD7
R452
Disabled as DEFAULT
TRACE_D1
PTD12
R190
Disabled as DEFAULT
TRACE_D2
PTD11
R435
Disabled as DEFAULT
TRACE_D3
PTD10
R511
Disabled as DEFAULT
All TRACE signals are DISABLED as default configuration. In order to enable the TRACE interface, the MCU signals routed to the QSPIA interface
must be disabled and isolated.