EasyManua.ls Logo

Onkyo DX-7511

Onkyo DX-7511
23 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
|
1
{Fox
|
1
|FoucsOk
input
|
2
{esw
|Ourpur
fitter
changeover
output
for
spindle
motor__|
MON
|_O
|Spindle
motor
controlouput
[4
|Mpp___|
©
|Spindle
motor
servoconrol
|
5
Imps
|
Oo
|
Spindle
motor
servo
control
LOCK
_|
©
|HwhenGFSisthehighlevel
ING!
ens
oN
eee
a
ee
vCOO
_|_0
JOscillation
circuit
output
for
analog
EFM
PLL.
>a
:
(8.6436MHz
Charge
pump
output
analog
EFM
PLL
round
terminal
om
QO
~~
LL
charge
pump
output
for
variable
pitch
Clock
input
for
variable
pitch
from
VCO
16.934MHz
iluer
output
for
master
PLL.
ist
rey
ee
i
G
[18
0
|
Cn
eee
ilter
input
for
master
PLL.
|
20
Or
lees
Ee
=
ee
ee
aw
es
ee
|*T
arge
pump
output
of
master
PLL
Og
ground
control
voltage
input
for
master
og
section
power
supply
(+5V
M
signal
input
|
symmetry
circuit
constant
current
input
symmetry
comparator
voltage
input
FM
full
swing
output
symmewy
control
circuit
|
©
B
x
~)
~)
|
~J
QO
S
ra
O
>
Audio
data
output
mode
changeover
input
Serial
data
at
L
and
paraller
data
at
H.
Out
DAL6
Serial
data
of
48
bits slot
DAIS
it
clock
of
48
bits
slot
A09
i
:
ae
B
2
:
42
_|DAO8
43
_{DA07
IDAOS
_|C2P0
output
45_|Daos
_|
47
_|DA03
DAO2
DAO2
DAO!
Ground
terminal
:
Crystal
oscillation
circuit
input
of
16.9344MHz
or
33.8688MHz
input.
Crystal
oscillation
circuit
output
of
16.9344MHz.
Crystal
selection
input
terminal.
L
when
16.9344MHz.
H
when
33.8688MHz.
2/3
divided
output
of
pins
53
and
54.
.2336
MHz
output
|
16.9344
MHz
output.
w
al
al
seer
hi
li
5
55
O
_
x
4
}
pital
output
control
input.
On
at
high
level.
Emphasis
control
output.
Active
high.
Write
frame
clock
output
Sub-code
detection
output.
H
when
is
detected
SO
63
Clock
input
for
read
out
SQSO.
Sub
Q
80
bits,
PCM
peak,
and
level
data
16
bits
outpul,
|
lock
input
for
read
out
SQSO
uling
control
output.
Active
H.
ens
Output.
Outpul
to
the
microprocessor
siem
reset.
Reset
at
the
low
level.
erial
data
input
from
the
microprocessor.
Latch
input
from
the
microprocessor.
Latch
the
serial
data
at
the
trailing.
Power
supply
treminal
Serial
data
latch
output
to
SSP.
Latch
at
wailing.
Oe
Serial
data
transfer
clock
output
to
SSP.
1
|
Mirror
signal
input
—__
Note:
SSP:1C10l
CXA1372Q
|
z
w
It
wn
res)
ID
S|
Ske)
SiRisis
isle
3
Ol*K
A
im
im
ia
x
oS
|e
81a
71
72
2)
S|
&
aa,
o]
3B
2
Oo
Ma
gy
"
5.
(2
©
i
:
:
re
o)
74HCUO04P
(Hex
inverters)
Vcc

Related product manuals