9.3. CD Servo Block
IC401 : YESAM275
Pin
No.
Port Descriptions I/O (V)
1 CVSS1 GND - 0
2 - - - -
3 CVSS2 GND - 0
4 DVDD1 I/O system (3.3V) power supply - 3.3
5 A10 Address bus of FLASH ROM O 0
6 - - - -
7 A11 Address bus of FLASH ROM O 3.3
8 A12 O 3.3
9 A13 O 3.3
10 A14 O 3.3
11 A15 O 3.3
12 /CVDD1 CORE CPU system (1.6V) power
supply
- 1.6
13 - - - -
14 DVSS1 GND - 0
15 CVSS3 GND - 0
16 /CVDD2 I/O system (3.3V) power supply - 1.6
17 - - - -
18 - - - -
19 READY - - 3.3
20 /PS FLASH ROM selection signal O 3.3
21 - - - -
22 - - - -
23 R/W Lead/light signal to FLASH ROM O 3.3
24 /MSTRB Memory access signal O 3.3
25 - - - -
26 /MSC - - 3.3
27 MUTE Mute signal output (H:Mute on) O 0
28 - - - -
29 - - - -
30 /HOLD - - 3.3
31 BIO SUBO input I 0
32 MP/MC Operation mode setting (external pull-
up)
I 3.3
33 DVDD2 I/O system (3.3V) power supply - 3.3
34 CVSS4 GND - 0
35 BD R1 GND I 0
36 - - - -
37 CVSS5 GND - 0
38 - - - -
39 - - - -
40 DVSS2 GND - 0
41 CLK C M AUDIO bit clock input I 1.6
42 SCK Clock input I 3.3
43 LRCK C
M
AUDIO L/R identifying signal input I 1.6
44 CDFS Serial frame sink signal input I 2.6
45 DATA
CM
AUDIO serial data input I 1.6
46 - - - -
47 SI Serial data input I 0
48 CLK M C AUDIO bit clock output O 1.6
49 SCK Clock input I 3.3
50 CVSS6 GND - 0
51 - - - -
52 CVDD3 CORE CPU system (1.6V) power
supply
- 1.6
53 LRCK M
C
AUDIO L/R identifying signal output O 1.6
54 CDFS Serial frame sink signal input I 2.4
55 - - - -
56 DVDD3 I/O system (3.3V) power supply - 3.3
57 DVSS3 GND - 0
Pin
No.
Port Descriptions I/O (V)
58 REST
SW
Mechanics deck REST SW input I 3.3
59 DATA M
C
AUDIO serial data output O 1.6
60 SO Serial data output O 1.2
61 - - - -
62 - - - -
63 /NMI - - 3.3
64 /INT0 - - 3.3
65 /INT1 - - 3.3
66 BLKCK Subcode block clock pulse input I 0
67 /INT3 - - 3.3
68 CV DD4 CORE CPU system (1.6V) power
supply
- 1.6
69 SW1 Mechanics deck SW1 input I 0
70 CVSS7 GND - 0
71 MCLK Clock output (To Servo DSP) O 3.3
72 DVSS4 GND - 0
73 MLD Command load signal output (To
Servo DSP)
I 3.3
74 MDATA Command data output (To Servo
DSP)
O 3.3
75 DVDD4 I/O system (3.3V) power supply - 3.3
76 DVSS5 GND - 0
77 CLK MD1 Clock mode setting (L fixation) I 0
78 CLK MD2 Clock mode setting (H fixation) I 3.3
79 CLK MD3 Clock mode setting (L fixation) I -
80 - - - -
81 SW2 Mechanics deck SW2 input I 0
82 - - - -
83 EMU0 - - 0
84 EMU/OF
F
- - 3.3
85 TDO - - 3.3
86 TDI - - 0
87 /TRST - - 3.3
88 TCK - - 0
89 TMS - - 3.3
90 CVSS8 GND - 3.3
91 CVDD5 CORE CPU system (1.6V) power
supply
- 0
92 HPIENA GND I 1.6
93 DVSS6 GND - 0
94 - - - -
95 CLKENA Oscillation output Cainabl signal O 3.3
96 X1 Crystal Connection O 0
97 X2/CLKIN Crystal Connection I 0
98 RS Reset signal input I 1
99 D0 Data base of FLASH ROM I/O 3.4
100 D1 I/O 0
101 D2 I/O 0
102 D3 I/O 0
103 D4 I/O 0
104 D5 I/O 0
105 A16 Address bus of FLASH ROM O 0
106 DVSS7 GND - 0
107 A17 Address bus of FLASH ROM O 3.3
108 A18 O 0
109 A19 Address bus of FLASH ROM O 0
110 A20 O 0
111 CVSS9 GND - 0
112 DVDD5 I/O system (3.3V) power supply - 3.3
113 D6 Data bus of FLASH ROM I/O 0
114 D7 I/O 0
115 D8 I/O 0
116 D9 I/O 0
117 D10 I/O 0
6
CQ-C1401U / CQ-C1301U
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