Panasonic DMR-BWT955GL - Digital P.C.B. Block Diagram (1;2)

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11.4. Digital P.C.B. Block Diagram (1/2)
IC51001
(HDDEC/ENC/CPU/GFX Process/DDR3-IF/RTSC/AVCore/Graphics)
IC51301
(8bit NAND)
64M X 8bit NAND
FLASH MEMORY
TC- 1 BUS_ED0-7_B
HOST I/F
USB2DN
USB2DP
USB1DN
USB1DP
USB0DN
USB0DP
V33
V33
AF34
AF33
PW_5V_VBUS_2
2
1
3
(Front USB)
P59302
DN
DP
VBUS
WIRELESS
MODULE
3
P59304
2
P59304
TS_SYNC
IC8202
CHIP CHANNEL RECEIVER
CH0PSYNC
CH0VAL
CH0CLK
CH0DATA
G_SDA1_B
G_SCL1_B
XFERSTB
TS_VAL
TS_CLK
TS_DATA
8
7
9
11
SDA_HOST
5
SCL_HOST
RESETB
RESETB
4
22
A26
C26
B25
B26
G_CH0PSYNC
CKG_CH0CLK
G_CH0DATA
G_CH0VAL
DIGITAL BLOCK DIAGRAM(1/2)
IF+_B
29
30
34
SCL
SCL_MAST
SDA_MAST
ADC_IP
ADC_IN
33
SDA
8
5
4
TU8201
9
TS_SYNC
IC8204
CHIP CHANNEL RECEIVER
CH1PSYNC
CH1VAL
CH1CLK
CH1DATA
G_SDA1_B
G_SCL1_B
XFERSTB
TS_VAL
TS_CLK
TS_DATA
8
7
9
11
SDA_HOST
5
SCL_HOST
4
22
C28
SDA1
E26
SCL1
F26
XFERST
D26
B28
A27
C27
G_CH1PSYNC
CKG_CH1CLK
G_CH1DATA
G_CH1VAL
30
29
34
SCL
33
SDA
8
14
15
9
TO
TUNER P.C.B.
B12
A12
MM0CK
MM0XCK
IC52000
IC52001
DDR SDRAM
1Gbit
DDR SDRAM
1Gbit
MM0DQ 16-31, MM0A 0-14
MM0DQ 0-15, MM0A0-14
DDR3_I/F
J7
K7
J7
K7
CK
/CK
CK
/CK
K3
MM1CK
K2
MM1XCK
IC52203
DDR SDRAM
1Gbit
MM1DQ 0-15, MM1A 0-13
J7
K7
CK
/CK
IC59001
( ETHERNET CONTROLLER)
2
3
12
13
4
5
TX+
TX-
RX+
RX-
JK59001
ETHERNET & USB JACK
TX+
TXP
TXM
RXP
RXM
TX-
RX+
RX-
HOST I/F
MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
13
RXD3
14
RXD2
15
16
RXD1
RXD0
24
TXD0
25
TXD1
26
TXD2
27
TXD3
RGMII_RXCLK
19
RXC
MII_RXER
20
RXER
RGMII_RXCTL
18
RXDV
MDIO_INTL
21
INTRP
XETH_RST
10
REXT
RGMII_TXCTL
23
TXEN
RGMII_TXCLK
22
TXC
MDC
12
MDC
MDIO
11
MDIO
AL32
AL33
AP31
AP33
AN34
AN33
AK31
AK33
AN32
AK34
AJ34
AJ33
AJ32
AG29
AP32
7
6
5
4
DMR-BWT955GL
AM33
AM32
VIDEO REC SIGNAL
VIDEO EE SIGNAL
VIDEO PB SIGNAL
AUDIO REC SIGNAL
AUDIO EE SIGNAL
AUDIO PB SIGNAL
SCL_MAST
SDA_MAST
ADC_IN
ADC_IP
AP11
AN11
AF32
AG33
TU8201
TU8201
TU8201
IF-_B
IF+_BIF+_BIF+_B
IF+_A
IF-_A
TU8201
TU8201
TU8201
TU8201