Panasonic DMR-PWT550GL - Analog Timer Block Diagram

78
11.2. Analog Timer Block Diagram
IC59501
(TIMER)
IC59505
(RESET)
IC59502
(RESET)
1
OUT
1
OPEN/
CLOSE
S7201
IR7201
REMOTE CONTROL
RECEIVER
OUT
IC58401
(RESET)
HDD_PFAIL_L
1
OUT
32
11
PFAIL[L]
FL_TXD
FL_CLK
RESET
3
1
31
KEYIN3
KEYIN1
REMOCON
DIGITAL P.C.B.
FRONT P.C.B.
P7201
9
10
P6702
P6703
P58813
P7201
812
P6702 P6703 P58813
P7201
10 6
P6703
P58813
1
32
15
16
X59501
10MHz_IN
10MHz_OUT
13
12
32.768KHz_OUT
32.768KHz_IN
33
HDMI_MONI(CEC_IN)
39
HDMI_CEC_OUT
10MHz
X59502
32.768KHz
Q59503
Q59506,
SWITCHING
BUFFER
JK55001-13PIN
P58813
54
P6703 P6702 P7201
P58813
3
2
4
P6703 P6702 P7201
3
P6702 P7201
70
68
40
57
34
48
60
50
77
JC_P_ON[H]
JC_P_ON_H
37
HDMI_P_ON[H]
HDMI_P_ON_H
78
JC_P_ON_DL_H
JC_P_ON_DL_H
XMPREQ
G_SCLK_A
G_XINTP_A
G_XINTM_A
IC51001
(HD DEC/ENC/CPU/GFX Process/
DDR3-IF/RTSC/AV Core/Graphics)
VDD
GND
IR
PW_XN_3.3V
PW_X_SW12.0V
MAIN P.C.B.
Q59505
P58813 P6703
FRONT P.C.B.
TO DIGITAL P.C.B.
REGULATOR BLOCK
DIAGRAM
P_STANDBY_H
JC_P_ON_H
HDMI_P_ON_H
JC_P_ON_DL_H
P_STANDBY_H
XINTM_OUT
XINTP_OUT
TBUS_CLK
XINTM[TBUS]
XMPREQ[TBUS]
TBUS_TXD
TBUS_RXD
XRES_PKS
PKS_STATE
AK4
AL3
AP2
XINTM
XINTP
SCLKM
AP4
XRST
AP4
XSRST
SD_BOOT
AL4
SDBOOT
Q59501,Q59502
P58810
1
P58810
3
FAN MOTOR
Timer Block Diagram
58
G_SBPTM_A
59
G_SBMTP_A
61
75
66
AJ4
XMPREQ
AP3
AN4
SBPTM
SBMTP
76
36
FANLOCK
FAN_DA
FL_CS
69
38
HDD_PFAIL[L]
41
DR_P_ON[H]
DR_P_ON_H
DR_P_ON_H
IC7201
DP7201
(DISPLAY DRIVE)
7
DIN
8
CLK
9
13
STB
VDD
FL_3.3V
SG1
SG4
14
17
GR1
GR7
42
31
1G
7G
5
9
SG5
SG16
29
P1
P16
31
8
16
DMR-PWT550GL/GZ
S7202
POWER
P7201
7
11
P6702
P6703
P58813
P6702