Panasonic TH-50PZ850U - Block Diagram (3;6): Signal Processing

33
9.3. Block Diagram (3/6)
CH0DATA
Q5604
+5V(S)
D5692
D4809
+3.3V(S)
+3.3V(S)
+3.3V(S)
L4801
+9V(S)
+30V(BT)
D4803
3.3V(STB)
D7800
+15V(SND)
9V(S)
L4802
D2301
+1.2V(S)
Q5603
5V(STB)
+5V(S)
5V(S)
+30V(BT)
+5V(S)
+3.3V(S)
+1.8V(S)
Q4802
D5612
D5611D5613
Q7701
Q7700
Q8500
(LED:12TIMES)
(LED:12TIMES)
FSTB+15V DET
SUB MONO
L+R
NAND FLASH
Q2301
PWM
5
IC5402
EEPROM
D1_R
SOUND
PROCESSOR
G
1
DTV RESET
CONV.
PCI-BUS
OUT
TV_R
OUT
IIC1
IIC0
G51
DDR2 #0-#3
CONV.
7
V2_L
SOS
OUT
RESET
AUDIO
PROCESS
7
4
SUB+3.3V
CONV.
+1.2V(S)
MAIN
OUT
(TS)
A10
IC2106
Y/C/V
OPTICAL
+3.3V
DIGITAL
DEMODULATOR
ON/OFF
2
D/A
IC3001
OUT
V2_V
AFT
IC2302
D/A
PC_L
SQUAWKER_R
+5V
L_OUT
AUDIO AMP R
PC_G
A/D
WOOFER
JK3001
D2_R
SQ_L(-)
V2_L
L/R
SQ_L
PC
AUDIO
DTV-SDIN
W_L
KEY SWITCH
ERROR DET
SQ
MON_L
WOOFER
D+
SQUAWKER_L
PC
PC_R
W_L(+)
SQ
VIDEO4
STB
+3.3V
W_L(-)
PC_B
L/R
PC_H
D2_PB
HDMI-SDIN
+15V
V2_L
L_OUT
TU8300
JK3000
PC_R
V1_C
1
3
PC
IC8500
L/R
PC_V
SQ_L(+)
SUB+1.8V
Y/UV_16bit
V1_L
R_OUT
PC
MONITOR
OUT
WOOFER_L
CPU BUS I/F
STB3.3V
R_OUT
1
DTV1
OSD_16bit
MON_R
OPTICAL
MON_V
AUDIO AMP L
11
IFD_OUT2
L/R
PRO
JK3000
TV
5
DTV_L/R
+1.8V(S)
IC8001
D1_L
A9
STB
IC5603
W_R
3
MAIN L/R
+1.2V
9
SUB
OUT
RESET
CARD DET
V1
10
+15V
SQ_R(-)
11
ERROR DET
V2_C
W_R(+)
DTV_V
DTV2
3
1
12
SOUND SOS
5
V2_V
DTV-SDIN
TUNER
13
IIC_TU
SQ_R
R/G/B/H/V
IIC1
11
TV_V
KEY SWITCH
D1
TRANSPORT
DECODER
TV
IF_AGC
AV_L/R
TV_L
+9V(S)
+5V(S)
HDMI-SPDIF
HDMI SOUND
IC5601
IIC1
VIDEO4
DDR I/F
COMP2
IC8506
DIGITAL SIGNAL PROCESSOR
V
L/R
+9V
MON
+30V(BT)
Y/PB/PR
L/R
V2_V
IC8201,02,03,04
+3.3V(S)
V2_R
D3005
4
CONTROL
V2
WOOFER_R
+1.8V
4
D1_PR
PC
A
+1.8V
VIDEO2
L/R
+3.3V(STB)
D1_PB
TV
VIDEO1
STB_RESET
HS/VS
PC_HS/VS
OUT
IIC_IF
SUB+1.2V
IC8300
1
AV L/R
VIDEO2
D1
VIDEO1
VIDEO3
(TERRESTRIAL RECEIVER)
V2_Y
9
HS/VS
DTV_R
D2
Y/PB/PR
IF_AGC
DTV1
+1.8V
W_R(-)
AUDIO
DTV_L
PC
Y/PB/PR
D2_Y
AUDIO
SQ_R(+)
V2_R
FRONT END PROCESSOR
IC5600
FSTB+15V
IC2107
VIDEO
PROCESS
+1.2V(S)
1
Y/C
V2_C
2
AFT
+3.3V
VIDEO2
IC2008
3
VIDEO1
4
DTV_V
D2
+30V(BT)
5
MONITOR
FRONT TERMINAL
IC4800
SOUND PROCESSOR
6
+3.3V(S)
COMP2
+3.3V(S)
STB_RESET
7
IC2301
+5V(S)
8
D2_PR
Peak s
V2_Y
L/R
KEYSCAN1
SPDIF-IN
VIDEO
COMP1
COMP2
D2_L
Y/C/V
COMP1
A51
+15V(SND)
TV
RESET
SPDIF-IN
JK3701
KEYSCAN3
PCI BUS
V1
V1_V
2
ANT IN
+9V
V
COMP1
RGB_CVBS
V2_R
VIDEO SW
CLOCK
L/R
IFD_OUT1
MUTE
SOUND
SOS
DET
IIC_TU
SD BLUE LED
L/R
V2_Y
3
V1_Y
GL
KEYSCAN1
A12
SD BLUE LED
SPDIF-OUT
AUDIO SW
OSD
PROCESS
2
GL
02
+3.3V
ANALOG ASIC
V2
D1_Y
FSTB
+15V
MON
VIDEO3
V2_C
9
Y/PB/PR
Y/C
Y/PB/PR
V1_R
SPDIF-OUT
I/F
OSD_16bit
+3.3V
PROTECT
OVER_CURR
USB
DECODER
VDD
SCLK
CTRL25
+2.5V
IIC
RUN
CONTROLLER
X1
IC8504
USB IF
IC8502
ETHER NET IF
SD CARD
JK7702
+3.3V
USB
ENCODER
SD CARD
I/F
IC7700
DRAM
VDD
SD DATA
4bit
SD DTC
GS
02
1
IC7702
SD CARD I/F
SBI0
SBO0
RXD0
TXD0
CLK2
CLK3
VDD
CLK1/4
IC8101
CLOCK GEN.
6
+3.3V
IC7701
4
GS09
6
2
3
D-
+5V
IC8505
+5V
GS SD CARD SLOT
SD LED
EEPROM
IC8503
JK8500
ETHER
NET RUN
RX+/-
TX+/-
GC6 RST
PCI-BUS
32bit+4bit
PCI-BUS
32bit+21bit
+5V(STB)
IIC1
14
CPU BUS
Y/UV_16bit
GC6 RST
SDWP
USB/LAN
D+
D-
CPU BUS
BOOT ROM
IC8501
(LED:12TIMES)
TH-50PZ850U
Block (3/6) Diagram
TH-50PZ850U
Block (3/6) Diagram