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IC Data Sheets
EN 34 TPM15.1E LA8.
2015-Jun-12
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8.4 Diagram 10-4-13 DVB/T2/C/S2 Tuner B13, AVL6211LA (IC U104)
Figure 8-6 Internal block diagram and pin configuration
19600_304.eps
Block diagram
Pinning information
AADC_AVDD
ADC_AVDD
ADC_AVSS
ADC_IP
ADC_IN
ADC_QP
ADC_QN
PLL_AVDD
ADC_AVSS
PLL_AVSS
VDDC
VDDC
PLL_REFCLK_XI
GND
RFAGC
PLL_REFCLK_XO
VDDC
GND
MPEG_ERR
MPEG_SYNC
MPEG_VALID
VDDIO
GND
VDDC
MPEG_CLK
MPEG_DATA_0
MPEG_DATA_1
GND
VDDIO
VDDC
VDDIO
TDI
TDO
TCLK
GND
TMS
TRST_N
VDDC
MPEG_DATA_7 MPEG_DATA_6
GND
VDDIO
GND GND RST_B CS_0 LNB_CNTRL_1 LNB_CNTRL_0
DISEQC_OUT VDDC VDDIO DISEQC_IN SDA2 SCL2
G
N
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
17
18
19 20 21 22 23 24 2
5
26 27 28 29 3
0
31
35
36
37
38
39
40
41
42
43
44
45
46
47
48
52 53
54 55 5
6
57 58 59 60 61 62 64
GPIO_CLK
LOCK
AVL6211LA
TOP VIEW
(Not to Scale)
MPEG_DATA_5
15
16
MPEG_DATA_4 32
MPEG_DATA_2
33
34
SDA1 SCL150
51
MPEG_DATA_3
SLEEP49
63
AVL 6211
Dual
10 - Bit
ADC
PLL
Digital Front-end
Down Converter
Carrier
Phase
Recovery
Symbol
Timing
Recovery
Equalizer
PL Frame
Processor
DVB FEC
Viterbi/RS
Decoder
TS Output
Interface
Tuner
Control
Interface
DiSEqC
2.0
Control
Interface
Two-wire
Bus
Controller
RFAGC
ADC_I
ADC_Q
MPEG TS
Output
JTAG
LDPC &
BCH FEC
Decoder