Philips 40PFL8008S/12 - Page 151

Circuit Diagrams and PWB Layouts
EN 151QFU1.2E LA 10.
2014-Jan-10
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div. table
10-3-9 B02D, DVBS/S2 channel decoder
19370_093_130222.eps
130222
DVBS/S2 channel decoder
B02D B02D
2013-01-11
6
2012-11-08
5
3104 313 6618
DVBS/S2 channel decoder
COM
OUTIN
NC
GND_HS
TS_ERR|GPIO_1
TS_CLK
TS_DATA0|TS_SER
TS_DATA1
TS_DATA2
TS_DATA3
TS_DATA4
TS_DATA5
TS_DATA6
TS_DATA7
SDA_HOST
SCL_HOST
VIA
S_ADC_QP
S_ADC_QN
MP_A
MP_B
MP_C
MP_D
TC_ADC_P
TC_ADC_N
SDA_MAST
SCL_MAST
DISEQC_CMD
DISEQC_IN
DISEQC_OUT
GND1|JTAG_TCLK
GND2|JTAG_TDI
GND3|JTAG_TDO
GND4|JTAG_TRSTB
GND5
VDD_VANA
VDD_VIO
VDD_VCORE
TS_SYNC
TS_VAL
XTA_I|CLK_IN
XTA_O
CLK_IN_OUT
RESETB
GPIO_0|JTAG_TMS
ADDR
RSSI_ADC
S_ADC_IP
S_ADC_IN
1
3
2
4
LD1117S33
7RDA
2RD8
IRDA
100n
IRD0
1 83RD6
10K
3RD0-1
47R
3RD1
47R
100n
2RDH
+3V3-DEMOD
FRDA
47R
3RD8
DRD1
5RDA
30R
10n
2RDN
2RD1
100n
2RDA
100n
4
1 3
1RD0
NX3225JB
16M
2
2RDC
6p8
4K7
3RDB
RES
RES
3RD4
47R
22u
2RDS
IRD1
DRD0
3RD2
10K
RES
3RDA
4K7
1K0
3RD9
5RDB
+1V2-FE
30R
+3V3-DEMOD
+V-LNB
53
54
55
56
57
58
33
32
+3V3-DVBS
36 7 20 28 48 9 22
50
51
52
17
18
19
23
24
25
26
13
12
45
38
37
40
39
42
41
14
15
16
49
3
1
2
29
30
31
43
10
46
11
34
44
4
5
6
8
21
27
47
35
SI2169-A10-GM
7RD0
9RD3
+5V
100p
2RDT
5RDD
30R
2RD4
100n
100n
2RD3 2RD0
100n
3RD7
47R
9RD0
IRD6
+3V3-ANA
2RD6
100n
5RDC
30R
2RD2
100n
27
+3V3-DVBS
47R
3RD0-2
22u
2RDM
IRD5
100n
2RDP
2RDDRES
10p
+3V3-ANA
9RD2
16V22u
2RDR
100n
2RD7
IRDC
22u
2RDJ
2RDL
22u
RES
2RDF
100n
+3V3-DVBS
100n
2RD9
22u
2RDK
IRD2
RES
47R
3 6
IRDB
3RD0-3
100n
+3V3-DEMOD
2RDB
47R
3RD5
+3V3-DEMOD
2RDG
100n
2RD5
10K
3RD3
100n
IRD3
9RD1
AGC-SWITCH
SDA-S-TUNER
SCL-S-TUNER
RES 2RDE
10p
DVBS-AGC
F22-DISECQ-TX
DVBS-IN
IF-P-DVBT2
IF-N-DVBT2
IF-AGC-DVBT2
XTAL
TS-DVBS-DATA
TS-DVBS-CLK
TS-DVBS-SOP
TS-DVBS-VALID
RESET-FUSION-OUTn
DVBS-QP
DVBS-QN
DVBS-IP
SCL-FE
SDA-FE