Philips 40PFT6550/12 - Page 54

IC Data Sheets
EN 54 QM15.2E LA8.
2015-Sep-30
back to
div.table
8.6 Diagram 10-6-10 MHL/HDMI Input, B10, Si2166-B22 (IC U201)
Figure 8-7 Internal block diagram and pin configuration
19790_303.eps
Block diagram
Pinning information
Si2166
Si2166B
(GND_PAD)
QFN-48
7x7mm
343536
21
22
23
24
3 4 5
33
20
6
32
7
28293031 27
8 9 10 11 12
15
16
17
18
19
40
39
38
37
41
46
45
44
43
42
MP_A
S_ADC_IP
S_ADC_IN
S_ADC_QP
S_ADC_QN
SDA_MAST
SCL_MAST
NC
NC
NC
DISEQC_OUT
MP_B
SCL_HOST
DISEQC_CMD
GND
SDA_HOST
TS_VAL
DISEQC_IN
TS_DATA[1]
TS_DATA[5]
TS_DATA[4]
TS_DATA[3]
GND
VDD_VIO
TS_DATA[2]
TS_DATA[0]/TS_S
TS_CLK
TS_SYNC
47
14
TS_DATA[7]
RESETB XTAL_I/CLK_I XTAL_O GND VDD_VCORE
VDD_VANA
ADDR
GND
GPIO_0
48
13
21
26 25
TS_DATA[6]
TS_ERR/GPIO
CLK_IN_OUT
GND
VDD_VCORE
VDD_VCORE
VDD_VIO
VDD_VCORE
MP_D
MP_C
HDTV MPEG S.o.C.
Si2166B
HOST_SCL
HOST_SDA
FRONT
END
OSC
& PLL
QPSK
8PSK
DEMOD
S_ADC_IN
S_ADC_IP
S_ADC_QN
S_ADC_QP
ADC (I)
ADC (Q)
EQUAL-
IZER
I
2
C
SWITCH
TUN_SDA
TUN_SCL
GPIOCTRL
MPEG TS
INTERFACE
I
2
C
I/F
MP_x
GPIO_0
RESETB1.2, 3.3V
DSP &
SYNCHRO
DVB-S/S2
FEC MODULE
DiSEqC
TM
2.0
DISEQC_IN
DISEQC_OUT
AGCs
Ext. Clk or Xtal
QPSK / 8PSK
Satellite
ZIF Tuner
CLK_IN_OUT
LDPC BCH
VITERBI RS
TS_ERR/
GPIO_1
TS_SYNC
TS_VAL
8
TS_CLK
TS_DATA