Philips BDP5506 - Page 33

1-11-3
E5WA0BLD2
Digital Signal Process 2 Block Diagram
K7
J7
K6
J1 J2
K1 K2
L1 L2
M2 M1
T29 T30
R29 R30
A14
D10 C10
A11 E12
F12
G14 G12
E10
BD MAIN CBA UNIT
USB CBA
WiFi CBA
ED (0-7)
MII-RXD (0-3), MII-TXD (0-3)
C0DQ (0-31)
C0A (0-13)
C1DQ (0-15)
C1A (0-13)
MEDIA PROCESSOR
Java (BD-J) MPEG-2 DiVX VC-1 H.264 DECODER HD (TS) SD (PS)
SD CARD SLOT
USB JACK
FROM DIGITAL SIGNAL PROCESS 1 BLOCK DIAGRAM (IC6001)
ETHERNET INTERFACE
CN6401
CN1302 CN1402
CN1301
CN6403
MEMORY I/F
SD I/F
IC6001 (MAIN MICRO CONTROLLER/DIGITAL SIGNAL PROCESS)
IC6305
(NAND FLASH MEMORY)
(ETHERNET JACK)
NAND FLASH MEMORY (2Gbit)
(DDR3 SDRAM) IC6201,IC6202
DDR3 SDRAM (1Gbit )
(DDR3 SDRAM) IC6203
DDR3 SDRAM (2Gbit)
Y27-Y29, AA24
I/P CONVERTER /SCALING
DIGITAL VIDEO OUT
HDMI I/F
DIGITAL AUDIO OUT VIDEO DAC
USBDP1 USBDN1 USBDP0 USBDN0
SD DATA(0-3)
TO VIDEO/AUDIO BLOCK DIAGRAM
VIDEO
MC MD
DAC-SCK DAC-BCK
DAC-LRCK
MS1
DATA
SPDIF
TO VIDEO/AUDIO BLOCK DIAGRAM
VIDEO SIGNAL AUDIO SIGNAL
IC6501
TX(+) 1
TX(-) 2
RX(+) 3
RX(-) 6
CN6501
T.M.D.S DATA2- T.M.D.S DATA2+ T.M.D.S DATA1- T.M.D.S DATA1+ T.M.D.S DATA0- T.M.D.S DATA0+ T.M.D.S CLOCK+ T.M.D.S CLOCK-
JK6401
HDMI-CONNECTOR
DDC DATA DDC CLOCK
HOT PLUG DETECT
19 15 16
3 1 6 4 9 7
10 12
4
4
USBDP1
3
3
USBDN1
CN6402
4
4
USBDP0
33USBDN0
WIRELESS LAN MODULE