Reflex
Service Manual
Theory
of Operation
Power Fail/Reset
Reset
signaling
is
controlled
by the
+5VUNREG voltage.
If the
+5VUNREG
voltage
at
the
input
of the
+5V
regulator
(U1
7)
is
high enough
to
create
a
2
volt
or greater drop
across
the regulator (regulator dropout voltage
=
2.0V
=
Vin
-
Vout) then the
differential between the voltage
divider
(R29
and
R30)
at
the
emitter of
Q4,
and the regulated
+5VD
at
the base
of
Q4
will
be
enough to
turn
on
Q4.
As
Q4 turns on,
the
voltage
across
R31 goes
from
OV
to
about
+6V. This
voltage is the
signal
that allows the
quad
latch
(U16)
which
generates
the
reset states to be
cleared (power-down/brown-out) or
have the reset
states
clocked
through
(power-up)
by
the monostable
multlivibrator
circuit (R22,
C15,
andU11).
During
power down or brown-out
all
reset
signals occur
simultaneously as
Q4
turns
off
and clears
the
reset latch
(U16).
On power-up the
action
of the
various reset
signals
is sequential.
This
is
due to
the
quad
latch
(U1
6)
clocking
its output
states
back through
as
inputs
as
desribed
below.
Once the -i-5V
digital
rail
is stabilized and the multivibrator is
running,
the
Lexichip II
(U1
4)
and
the
UART
(U2)
will
come
out
of reset
(LRST/
and URST)
.
This
occurs
well
after (more than 230ms) the
Lexichip crystal
starts
running
.
URST
also
clears
the interrupt
timer
so,
once the word clock
is generated,
there will
be
one
complete interrupt period clocked through
before
the
Z80
NMI
has
to be
enabled.
70ms afterthis occurs,
the Z80
will
come out
of reset
(ZRST/).
The Z80 needs
to
come
out
of
reset
after the
Lexichip II
is
running
because
the
Z80
derives
its clock
from
the
Lexichip.
As the
Z80
comes out
of
reset, the
output
registers
are
enabled
(DISPLAYEN/),
so
the
Z80
can
write
to
the display,
control
the
EEPROM
clock
for the
reset circuit and disable the
NMI.
The
reset
circuit
proceeds
normally,
as
on power-up. EEPCLK is
pulled
low
by a
1
0kQ resistor
(R78), allowing
U1 6to
be
clocked
by
the
oscillator
until
the
Z80 writes
EEPLCK
as
high.
EEPLCK
is
written
high
when
the
Z80
comes
out
of reset, disablingtheoscillatorfromclockingthrough
RSTMUTE/
signal. This
is accomplished
by
gating the oscillator
output
with
the
EEPCLK
signal
using
an
AND
gate
(U42).
The RSTMUTE/ signal
will
now
get set
the
first time
the
EEPROM
gets
written
to
or
EEPCLK
goes
low for
two oscillator
periods.
This
will
be
sometime after the
power-up diagnostics have run and the
WCS
is
initialized.
Reset,
System Processor,
Memory Mapping,
Interrupt Timer
4-3
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