Renesas RX110

RX Family ADC Module Using Firmware Integration Technology
R01AN1666EJ0220 Rev. 2.20 Page 16 of 74
Dec 01, 2016
/* for ADC_CMD_ENABLE_CHANS */
// Bitwise OR these masks together for desired channels
#define ADC_MASK_CH0 (1<<0)
#define ADC_MASK_CH1 (1<<1)
#define ADC_MASK_CH2 (1<<2)
#define ADC_MASK_CH3 (1<<3)
#define ADC_MASK_CH4 (1<<4)
#define ADC_MASK_CH5 (1<<5)
#define ADC_MASK_CH6 (1<<6)
#define ADC_MASK_CH7 (1<<7)
#define ADC_MASK_CH8 (1<<8)
#define ADC_MASK_CH9 (1<<9)
#define ADC_MASK_CH10 (1<<10)
#define ADC_MASK_CH11 (1<<11)
#define ADC_MASK_CH12 (1<<12)
#define ADC_MASK_CH13 (1<<13)
#define ADC_MASK_CH14 (1<<14)
#define ADC_MASK_CH15 (1<<15)
#define ADC_MASK_CH21 (1<<21)
#define ADC_MASK_GROUPB_OFF (0)
#define ADC_MASK_ADD_OFF (0)
typedef struct st_adc_ch_cfg // bit 0 is ch0; bit 15 is ch15
{
uint32_t chan_mask; // channels/bits 0-15, 21
uint32_t chan_mask_groupb; // valid for group modes
uint32_t add_mask; // valid if add enabled in Open()
} adc_ch_cfg_t;
/* ADC_READ() ARGUMENT DEFINITIONS */
typedef enum e_adc_reg
{
ADC_REG_CH0 = 0,
ADC_REG_CH1,
ADC_REG_CH2,
ADC_REG_CH3,
ADC_REG_CH4,
ADC_REG_CH5,
ADC_REG_CH6,
ADC_REG_CH7,
ADC_REG_CH8,
ADC_REG_CH9,
ADC_REG_CH10,
ADC_REG_CH11,
ADC_REG_CH12,
ADC_REG_CH13,
ADC_REG_CH14,
ADC_REG_CH15,
ADC_REG_CH21,
ADC_REG_TEMP,
ADC_REG_VOLT,
ADC_REG_DBLTRIG,
ADC_REG_MAX = ADC_REG_DBLTRIG
} adc_reg_t;
#define ADC_REG_ARRAY_MAX (17)
/* ADC_READALL() ARGUMENT DEFINITIONS */