Basics on I/Q Data Acquisition and Processing
R&S
®
FSWP
20User Manual 1177.5856.02 ─ 07
The A/D converter samples the IF signal at a rate of 200 MHz. The digital signal is
down-converted to the complex baseband, lowpass-filtered, and the sample rate is
reduced. The analog filter stages in the analyzer cause a frequency response which
adds to the modulation errors. An equalizer filter before the resampler compensates
for this frequency response. The continuously adjustable sample rates are realized
using an optimal decimation filter and subsequent resampling on the set sample rate.
A dedicated memory (capture buffer) is available in the R&S FSWP for a maximum of
400 Msamples (400*1000*1000) of complex samples (pairs of I and Q data). The num-
ber of complex samples to be captured can be defined (for restrictions refer to Chap-
ter 4.1.1, "Sample Rate and Maximum Usable I/Q Bandwidth for RF Input",
on page 21).
The block diagram in Figure 4-1 shows the analyzer hardware from the IF section to
the processor.
Figure 4-1: Block diagram illustrating the R&S
FSWP signal processing for analog I/Q data (without
bandwidth extension options)
Figure 4-2: Block diagram illustrating the R&S
FSWP signal processing for analog I/Q data (with
option B320)
Processing Analog I/Q Data from RF Input