Rohde & Schwarz NRPxxA Series - Structure of a SCPI Status Register

Remote Control Basics
R&S
®
NRPxxA(N)
144User Manual 1177.6017.02 ─ 05
Output queue
Error/event queue
&
&
&
&
&
&
+
&
Status byte
Service request
to controller at
transition from 0 to 1
1
0
2
3
4
5
x
7
1
0
2
3
MAV
ESB
RQS/MSS
7
Service request enable
Operation status
Standard event status
Questionable status
Device status
1
2
3
4
5
Figure 11-1: Status registers overview
1 = Chapter 11.3.3, "Status Byte (STB) and Service Request Enable Register (SRE)", on page 146
2 = Chapter 11.3.5, "Device Status Register", on page 148
3 = Chapter 11.3.6, "Questionable Status Register", on page 149
4 = Chapter 11.3.7, "Standard Event Status and Enable Register (ESR, ESE)", on page 151
5 = Chapter 11.3.8, "Operation Status Register", on page 152
The highest level is formed by the status byte register (STB) and the associated ser-
vice request enable (SRE) register.
The status byte register (STB) receives its information from:
●
Standard event status register (ESR)
●
Associated standard event status enable register (ESE)
●
SCPI-defined operation status register
●
Questionable status register, which contains detailed information on the device.
●
Device status register
11.3.2 Structure of a SCPI Status Register
Each SCPI register consists of five 16-bit registers that have different functions, see
Figure 11-2. The individual bits are independent of each other, i.e. each hardware sta-
tus is assigned a bit number which is the same for all five registers. Bit 15, the most-
Status Reporting System