Protocol analysis
R&S
®
RTP
881User Manual 1337.9952.02 ─ 12
"Damping"
Sets the damping factor, which is only relevant for second order PLL.
Remote command:
BUS<m>:CDR:PLL:ORDer on page 2127
BUS<m>:CDR:PLL:BWIDth on page 2126
BUS<m>:CDR:PLL:RELBwidth on page 2127
BUS<m>:CDR:PLL:DAMPing on page 2126
Initial phase sync.
Defines the phase reference for the first clock edge.
"First sample"
The first clock edge matches the first sample of the waveform at the
left border of the display.
"First data
edge"
The first clock edge matches the first edge of the data signal.
Remote command:
BUS<m>:CDR:SYNC on page 2127
Selected results
The PLL requires some time to synchronize to the phase of the data stream. You can
select when the CDR algorithm returns clock edges:
"After initial
sync."
The clock edges of the synchronization time are discarded; results
are gathered after initial synchronization of the CDR. Thus, meaning-
ful TIE measurement results can be obtained.
"All"
All clock edges are used.
Remote command:
BUS<m>:CDR:RESults on page 2127
Software CDRs
Couples the protocol CDR to the selected software CDR. For more information about it
see, Chapter 18.3, "Clock data recovery", on page 1056.
13.22.3.2 PCIe Gen 3 settings
Access: [Protocol] > "Setup" tab > "Protocol = PCIe" = "Generation = Gen3" > "DSP"
tab
At this tab, you can enable and define the equalization techniques used for the equali-
zation at the reciever side of the signal.
PCIe (option R&S RTP-K72/K73)
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