SMIQ Digital Standard 3GPP W-CDMA (FDD)
1125.5555.03 E-92.215
2.14.2.11 Synchronization and Trigger Signals
To generate the W-CDMA signals, a chip sequence is calculated and stored in the waveform memory of
the modulation coder (option SMIQB20). This chip sequence is automatically repeated (TRIGGER
MODE AUTO).
For measurements on receivers, trigger signals can also be used for synchronized sequences
(TRIGGER MODE RETRIG, ARMED_AUTO or ARMED_RETRIG).
The trigger signal is applied to the TRIGIN input of the PAR DATA connector. The chip sequence either
starts immediately after the active edge of this trigger signal or after a settable number of chips (EXT
TRIGGER DELAY). A retrigger (RETRIG) can be inhibited for a settable number of chips (EXT
RETRIGGER INHIBIT).
A trigger event can be triggered manually with EXECUTE TRIGGER or via the IEC/IEEE bus. A trigger
signal is always output at TRIGOUT 3 output of the SMIQ at the same time as a trigger event.
The SMIQ generates the following sync signals:
• a 0.667 ms slot clock
• a 10 ms radio-frame clock
• a marker signal to identify the periodic repetition of the generated chip sequence
• a marker signal to identify the periodic repetition of the generated enhanced chip sequence (only
available if Option SMIQB48 is installed)
• a marker signal to identify a restart of the system frame number (SFN Restart) after 4096 frames
(only available if Option SMIQB48 is installed and a BCH is generated).
The SMIQ can output a selection of two or three signals via connectors TRIGOUT 1 and 2 of the
PAR DATA connector.
The chip clock in the SMIQ is generated by a clock synthesizer in the modulation coder. All clock signals
are in sync with the unit’s 10 MHz reference. The chip clock is available at the SYMBOL CLOCK
connector. If required, the clock synthesizer in the SMIQ can use an external chip clock which is fed in via
the SYMBOL CLOCK connector.
To ensure reliable clock-synthesizer synchronization, the external clock must first be applied and the
correct SMIQ chip rate set (MODULATION – CHIPRATE VARIATION). The CLOCK SOURCE can then
be switched from INT to EXT.
Note: The set chip rate may not differ by more than 1% from the chip rate of the external signal.
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