Samsung S23A750D - Page 54

5. Wiring Diagram
5-4
Location
Block
Functions
LVDS connector
between the 1st and 2nd
floors
Connects the LVDS signal from the 1st floor to the 2nd floor
FPGA
Receives and bypasses the LVDS 4 channel input, creates the 148.5MHz
output, and puts the output into the M180 system clock on the 2nd floor
DDR3
Starts the scaler
Scaler
This main IC receives the external input and displays pictures on the screen.
B to B connector
between the 1st and 2nd
floors
Transmits the signals between the 1st and 2nd floors
DP
Stands for Display Port and offers a higher input port performance than a DVI
HDMI
Connects to an AV device or PC
LED Driver
Turns on the backlight of the LED panel
Flash
This IC is where MICOMs for the scaler and FPGA are saved.
10
Function + Bluetooth
Connects the Function Assy and BT module
11
FAN
Starts the fan
1
2
3
4
5
6
7
8
9