No Pin Name I/O Reset Value Description PAD
31 Vssi Vss - 3.3 V Gnd
32 DATA23 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
33 DATA24 I/O " CPU Data Bus 23 "
34 Vddp Vdd - 5V
35 DATA25 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
36 Vssp Vss - 5VGnd
37 DATA26 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
38 DATA27 I/O " CPU Data Bus 23 "
39 Vddo Vdd - 5V
40 DATA28 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
41 Vsso Vss - 5VGnd
42 DATA29 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
43 DATA30 I/O " CPU Data Bus 23 "
44 DATA31 I/O " CPU Data Bus 23 "
45 Vssi Vss - 3.3 V Gnd
46 LFIA0 / OP4 O H Line Feed Motor Phase A PHOB4, 4mA
47 Vddi Vdd - 3.3 V
48 LFIA1 / OP5 O H Line Feed Motor Phase /A PHOB4, 4mA
49 LFIB0 / OP6 O " Line Feed Motor Phase B "
50 LFIB1 / OP7 O " Line Feed Motor Phase /B "
51 TnRST I TAP Controller Reset PHIT
52 TMS I TAP Controller Mode Sel PHIT
53 TDI I TAP Controller Data In "
54 TCK I TAP Controller Clock "
55 TDO O TAP Controller Data Out PHOB4
56 AVdd Vcca - Analog 3.3 V
57 AVin[0] I - Analog Input 0 PICA
58 AVin[1] I - Analog Input 1 "
59 AVss Vssa - Analog Gnd
60 AVssAVin[2] I - Analog Input 2 PICA
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