Sansui CD-V1000 - CXD-1135 Digital Signal Processor Pin Functions

cD-v1006.
Description
of
Pin
Functions
(CXD-1135
Digital
Signal
Processor)
|
;
-
™
i
or
Pin Pin
‘i
Pin
Pin
3
No.|
Name
chad
Function
No.|
Name
a
Function
1
ESW
O
Spindie
motor
output
filter
time
constant
switching
48
RAW
O
|.
External
RAM
address
output.
ADDR11
output.
:
:
—+——
:
49
ane
|
mi
Write
enabie
signal
output
to
the
external
RAM
:
2
|
MON
OQ]
Spindle
motor
ON/OFF
control
signal
output.
(active
at
“‘L"’).
]
3
MDP
0
Spindle
motor
drive
output.
For
CLV-S
mode
rouch
50
RACS
|
al
Chip
select
signal
output
to
the
external
RAM
(active
control
and
CLV-P
mode
phase
control.
at
“’L’’)
Spindle
motor
drive
output.
For
CLY-P
mode
speed
51
CaM
|
o
|
X'tal
division
output.
f
=
42336
MHz.
a
|
MDS
G
control
+
+
:
52
Vss
—}
GND
(0V)
5
EFM
|
|
RE
amplifier
EFM
signal
input.
53
XTAI
X'tal
oscillator
circuit
input.
f
=
8.4672
MHz
or
6
|
ASY
O|
EFM
signal
slice
level
control
output.
ah
16.9344
MHz,
depending
on
the
selected
mode.
|
The
GFS
singal
is
sampied
at
WFCK/16;
if
“RR,
‘“H"
54
XTAO
O
X’tal
oscillator
circuit
output.
f
=
8.4672
MHz
or
7
LOCK
O
|
is
output
through
this
terminal.
If
'‘L'’
for
8
consecu-
4
{
16.9344
MHz,
depending
on
the
selected
mode.
_|
|
tive
times,
“'L""
is
output.
55
MD1
Mode
selection
inputs.
+
8
A]
vcoo
|0
oes
locked
to
the
EFM
signal,
5
=
a
Me
=al
j
Mode
—
input.
t
13.
9
Veo
—
[veo
faut
3
_|
ue
ode
selection
inputs
4
Audio
data
output
code
switching
input.
2's
comple-
|
10
TEST
t=
{0
V)
sa
SLOB
ment
output
at
‘’L’’,
and
offset
binary
output
at
‘'H"’.
iit
[Pp
O
|
EFM
signal
and
VCO/Z
phase
comparison
output.
Audio
data
output
mode
switching
input.
serial
out-
[12
Vst
—J
Ground
(0
V}
59
PSSL
put
at
‘’L’’,
and
parallel
output
at
‘’H"’.
_|
|
|
[
cpu
serial
data
transfer
clock
input.
Data
is
latched
Outputs
DAos
when
PSSL
=
‘‘H’’,
and
PLCK
when
13
CLK
ao
70
DAog
O
Whidk
at
the
clock
rising
edge.
_|
=
PSSL
=
"L".
_|
14
XLT
,
|
CPU
latch
input.
Latches
8-bit
shift
register
data
(seri-
7
DAw
10
Outputs
DAto
when
PSSL
=
‘‘H’’,
and
UGFS
when
al
al
data
from
the
CPU)
to
the
registers.
pas
PSSL
=
"LL".
15
DATA
CPU
serial
data
input.
|
Outputs
DA11
when
PSSL
=
‘'H’’,
and
GTOP
when
72
DA
O
PSSL
=
UL"!
16
XRST
System
reset
input.
Reset
is
performed
at
‘’L’’
input.
pene
sie
17
|
_CNIN
Tracking
pulse
input.
MOG:
=|
=a)
POWGEL
EN
18
SENS
|0|
Outputs
internal
condition
data
for
each
address.
DAi2
0
one
DAY
when
PES.
=.
“Hand:
RAV
when
Muting
input.
When
the
internal
register
ATTM
is
‘’L"’,
—
Sari?
19
MUTG
1
|
MUTG
sets
the
normal
condition
at
‘’L’’
input,
and
the
75
DAi3
e)
Outputs
DAI3
when
PSSL
=
‘‘H’",
and
CaLR
when
muted
condition
at
‘'H’’
input.
PSSL_=
UL".
23
SUBOQ
||
Subcode
Q
output.
DAia
0
Sees
DAt4
when
PSSL
=
‘’H’’,
and
C210
when
24
|
SCOR
|O]
Subcode
sync
SO
+
S1
t.
—
is
na
eon
A
Outputs
DA1s
when
PSSL
=
“'H”’,
and
C210
when
25
SQCK
I/O}
Subcode
Q
readout
clock.
77
DAis
O}
pss,
=
UL,
26
SQEX
|_|
SQCK
selection
input.
78
DAs
(10
Outputs
DAt6
(parallel
audio
data
MSB)
when
PSSL
28
GFS
O
|
Frame
sync
locked
condition
indicating
output.
=
"'H'',
and
DATA
when
PSSL
=
“'L"’.
29
DBos
I/O]
External
RAM
data
terminal.
DATAs
(MSB)
Strobe
signal
output.
176.4
kHz
at
DF
ON,
and
88.2
79
|
WDCK
|0
30
|
DBor
|Vo|
External
RAM
data
terminal.
DATA?
KAeSL
OE
OE
31
|
DBos__|1/0|
External
RAM
data
terminal.
DATAs
ao
|
Lack
||
Stobe
signal
output.
88.2
kHz
at
DF
ON,
and
44.1
32
DBos
10]
External
RAM
data
terminal.
DATAs
KHz
at
DF
OFF.
[
33
Vopo
|—|
Power
{+5
V)
NOTES:
C1F1:
C1
decoding
error
correction
condition
data
monitoring
output.
34
|
DBoa
/O|
External
RAM
data
terminal.
DATAa
C12:
C2F1:
C2
decodi
‘orrectio
dition
data
monitorin
35
DBo3
Ae
External
RAM
data
terminal,
DATA3
andes
MO
ear
oreo
courier
Hang
36
DBo2
/O|
External
RAM
data
terminal.
DATA2
C2F2:
‘
37
DBo1
JO}
External
RAM
data
terminal.
DATA:
(LSB)
C2FL:
Correction
condition
data
output.
‘’H'’
when
the
C2
line
un-
der
processing
cannot
be
corrected.
38
RA
O}
Ext
1
RA
dd
it.
ADDRo1
(L
=
Maeda
oss
Outen
cu
eed
C2P0:
-C2
pointer
indication
output.
Synchronized
to
the
audio
data
39
RAo2
|
ie)
|
Externa
RAM
address
output.
ADDRo2
ouptut.
40
RAo3
O
|
External
RAM
address
output.
ADDRo3
RFCK:
Read
frame
clock
output.
7.35
kHz
of
x’tal
system.
ay
RAoa
©
|
External
RAM
address
output.
ADDRoa
WECK:
Dareeun
clock
output.
7.35
kHz
when
locked
to
the
42
RAos
O
|
&xternal
RAM
address
output.
ADDRos
PLCK:
VCO/2
output.
f
=
4.3218
MHz
when
locked
to
the
FFM
143
RAos
|
0]
External
RAM
address
output.
ADDRos
aes
niaer
a
‘
:
Unprotected
frame
sync
pattern
output.
ma
Rao?
_|
0
|
externa
RAM
address
output.
ADDRo7
GTOP:
Frame
synchronization
protected
condition
indication
output.
45
RAog
O|
External
RAM
address
output.
ADDRos
RAOV:
+4-frame
jitter
absorbing
RAM
overflow/underflow
indicat-
46
|
RAoo
[0]
External
RAM
add
tput.
ADDR
ing;
OUIDUE.
Bs
—
cleat
alk
a
CALR:
Strobe
signal.
352.8
kHz
at
DF
ON,
176.4
kHz
at
DF
OFF.
[47
RAio
O
|
External
RAM
address
output.
ADDRi0
C210:
C210
turnover
output.
C210:
Bit
clock
output.
4.2336
MHz
at
DF
ON,
2.1168
MHz
at
DF
OFF.
DATA: Audio signal serial data output.