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IC BLOCK DIAGRAM & DESCRIPTION
IC701 LC587008 (4bit MICON)
Address
Pin No.
Function
Option
At reset
V
DD
V
SS
24
23
Power supply
V
DD
1
2
V
DD
22
21
LCD drive power supply
NON 1/1 bias
1/2 bias
1/3 bias
VDD
VDD1
VDD2
VSS
CUP1
CUP2
3
4
Switching pin used to supply the LCD drive voltage to the VDD1 and
V2PINS
DD
Connect a nonpolarized capacitor between CUP1and CUP2 when
1/2 or 1/3 bias is used
Leave open when a bias other than 1/2 or1/3 is used.
CFIN
Input
25
System clock oscillator connections
Ceramic resonator connection (CF specifications)
RC component connection (RC specifications)
External signal input pin (CFOUT isleft open)
This oscillator isstopped by theexecution of aSTOP or SLOW
instruction.
CF specifications
RC specifications
External
Specifications
Not used
CFOUT
Output
26
XTIN Input 20
XTOUT
Output
19
Referenc e calculation(cl ock specification s,LCD alternain g frequency),
system clock oscillator
32 kHz crystal resonator connection
65 kHz crystal resonator connection
This oscillator isstopped by theexecution of aSTOP instruction.
65k specifications
32k specifications
38k specifications
Not used
S1
S2
S3
S4
Input
27
28
29
30
Input-only ports
Input pins used to read datainto RAM
Built-in 7.8 msand 1.95 mschatter rejection circuits
Built-in pull-up/pull-down resistors
Note: The 7.8 ms and 1.95 ms times arethe times whenf 0 is
32.768kHz.
Transistor to hold
alow or high level
Selection of either
pull-up or pull-
down resistor
The pull-up orpull-
down resistor are
on.
These pins go
to the floatin g
state when
reset is cleared.
Note:
K1
K2
K3
K4
I/O
31
32
33
34
I/O ports
Input pins used to output read data into RAM
Output pins used to output datafrom RAM
Built-in 7.8 msand 1.95 msinput-mode chatter rejection circuits.
The selection of 7.8 or 1.95ms is linked to that forthe S ports.
Note: The 7.8 ms and 1.95 ms times arethe times whenf 0 is
32.768 kHz.
Transistors tohold
a low orhigh level
Selection of either
pull-up or pull-
down resistor
The pull-up orpull-
down resistors are
on.
These pins go
to the floatin g
state when
reset is cleared.
Note:
Input mode
Outpu t latch data is
set high.
M1
M2
M3
M4
I/O
35
36
37
38
I/O ports
Input pins used to read datainto RAM
Output pins used to output datafrom RAM
M4 is usedas the external clock input pinin Tm2 mode 3.
*The minimum period for the external clock is twice the cycle time.
Built-in pull-up/pull-down resistors
The same as K1 to
K4
The same as K1 to
K4
A1
A2
A3
A4
I/O
11
12
13
14
I/O ports
Input pins used to read datainto RAM
Output pins used to output datafrom RAM
Built-in pull-up/pull-down resistors
The same as K1 to
K4
The same as K1 to
K4
P1
P2
P3
P4
I/O
15
16
17
18
I/O ports
Function: The same as pins A1to A4
The same as K1 to
K4
The same as K1 to
K4
Pin
I/O
QIP-80
Pin No.
Function
Option
At reset
So1
So2
So3
So4
I/O
7
8
9
10
I/O ports
Function: The same as for pinsA1 to A4
Pins So1 toSo3 area alsoused for theserial interface.
Use of these pins inserial modecan be selected under program
cotrol.
Pin functions: SO1:Serial input pin
SO2:Serial output pin
SO3:Serial clock pin
The serial clock pin can beswitched between internal and external,
and between rising edge output andfalling edge output.
Tra nsis tors to hold
alowor high level
Selection of either
pull-up or pull-
down resistors
Internal serial clock
divisor selecti on
The same asfor K1
to K4
I1/1
II 1/2
III 1/4
N1
N2
N3
N4
Output
39
40
41
42
Output-only ports
Output pins used to output data from RAM
An alarm signal can be output from pin N4.(Note that this isonly
when the N4output latch islow.)
An alarm signal modulated at 1,2or 4 kHzcan be output.(These
frequencies are output when f 0 is 32.768 kHz.)
Acarrier signal can be output from N3.(Note that this is only
when the N3output latch islow.)
Pins N1 to N4
outpu t circuit
type:
Pins N1 to N4
output
level
The output levels on
pins N1 to N4 can be
specified as an option
INT
Input
6
Input ports
External interrupt request inputs
Input pins used to read data into RAM
Input detection can be performed oneither rising orfalling edges.
Built-in pull-up/pull-down resistors
Transistors to hold
a low or high level
Select ion of either
pull-up or pull-
down resist ors
Signal convers ion
(rising/f alling)
selectio n
RES
Input
5
LSI internal reset input
The reset input level can beselected to beeither high orlow.
Built-in pull-up/pull-down resistors
Note: The reset pulse must beat least 500us.
*Only when the
input resistor open
specificat ion is
selec ted
TST
Input
43
Test input
QIP80 products: Connect to Vss.
Chip products :Leave open orconnect to Vss.
Seg1,
Seg2 to
Seg35
Output
44,
45 to
78
LCD panel drive/general-purpose
output
LCD panel drive
STATIC
1/2 bias-1/2 duty
1/2 bias-1/3 duty
1/2 bias-1/4 duty
1/3 bias-1/3 duty
1/3 bias-1/4 duty
Types Ito V canbe specified asmask
options.
General-purpose output mode
CMOS
P-channel open drain
N-channel open drain
Types Ito III canbe specified asmask options.
LCD/g eneral -purpo se output contro l is handled by the segment PLA,
and thus program control is not required.
These pins support output latch control on reset andin standby
states when theoscillators are stopped.
Arbit rary combinat ions of LCD drive and general-p urpos e output s can
be used.
LCD driver/
general-purpose
output switching
LCD drive type
switching
STATIC
1/2 bias-1/2
duty
1/2 bias-1/3
duty
1/2 bias-1/4
duty
1/3 bias-1/3
duty
1/3 bias-1/4
duty
General-purpose
output circuit
switching
CMOS
P-channel
open drain
N-channel
open drain
Outpu t latch control
in standby modes
LCD drive
All segment s on
All segments off
*:Determined by
mask options
General purpose
outputs
High level
Low level
Determined by
mask options
Note:
When a
combinatio n of
LCD drive and
general-
purpo se
outpu ts,the
outpu t state is
eithe r:
All lit/hig h level
All off/low level.
These pins go to
the static drive
mode during the
reset
period.
Continued from preceding
page.
COM1
COM2
Output
2
1
LCD panel drive common polarity outputs
The table below shows how these pins are used depending on the duty
used.( values for alterna ting freque ncy reflect a typical specification of
32.768 MHz for f 0.)
COM1
Static duty
1/2 duty
1/3 duty
1/4
duty
The static drive
waveform is output
during the reset
period.
*There are cases
where the
alternati ng
frequenc y stops for
the CF,RC and
external clock
specifica tions.
(These cases differ
dependi ng on option
specifica t
ions.)
COM3
COM4
80
79
COM2
COM3
COM4
Alternation
frequency
32 Hz32 Hz
32 Hz
42.7 Hz
32
Hz
Note: A cross( X ) indicates that the pin is not used with that duty type.
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