VCC_P
VSS_P
VSS
RESET#
VCC
DBUS15
DBUS11
DBUS13
DBUS12
DBUS11
DBUS10
DBUS9
DBUS8
DBUS7
DBUS6
DBUS5
DBUS4
DBUS3
DBUS2
DBUS1
DBUS0
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
DOE#/MA9
DWE#
DRAS0#
VCC
VSS
Names Pin No. I/O Descriptions
VSSA 1.9 G Ground for analog circuits.
RSET 2 O
Reset. Internal current source generator. Connect this pin to
a 510Ω resistor to ground.
VREF 3 O
Output reference voltage. Connect to a 0.01-µF high -frequency
bypass capacitor to VSSA.
COMP 4 O
Compensation capacitance for low-pass filter on VDAC. Connect
to a 0.01-µF high-frequency bypass capacitor to VSSA.
VCM 5 O
ADC analog voltage reference. Connect to a 0.01-µF filter
capacitor to VSSA.
MIC1.MIC.2 6,7 I Microphone inputs.
VDDA 8 P 5.0V power supply for analog circuits.
AUX0[7:5] 10:12 I/O General-purpose programmable I/O.
AUX3[2:0] 13:15 I/O General-purpose programmable I/O.
LWR# 16 O RISC interface Write Enable (active-low).
LOE# 17 O RISC SRAM Output Enable (active-low).
CS0# 18 O Chip select 0 for SRAM (active-low).
CS1# 19 O Chip select 1 for SRAM (active-low).
CS3# 20 O Chip select 3 for SRAM (active-low).
LD[7:0] 21:28 I/O Data bus.
VCC 29.42.66.95.116 P Core power supply (2.5V).
XIN 30 I Crystal connection or input source of 27MHz. Must be 50% duty cycle.
XOUT 31 O Crystal connection or output drive of an input clock source.
VSS 32,41,65,97,117 G Ground for core.
LA[19:0] 33:40,43:54 O Address bus.
TDMFS 55 I Frame signal from CDROM.
TDMDR 56 I Data signal from CDROM.
TDMCLK 57 I Clock signal from CDROM.
TBCK 58 O Transmit clock when sending audio IIS data to external DAC.
SEL_PLL1 I
PLL mode select 1. Pulldown to ground to bypass PLL. Pullup to
VCC for optimal performance.
TWS O Audio strobe signal of IIS signals to external DAC.
SEL_PLL0 I
PLL mode select 0. Pulldown to GND to bypass PLL. Pullup to VCC
for optimal performance.
TSD O Audio data of IIS signals to external DAC.
MCLK 61 I/O
Media clock input to drive external audio devices or media clock
output when driven by external source into the ES 3890.
CAS# 62 O Column Address Strobe to DRAM (active-low).
DRAS1# 63 O Row Address Strobe 1 to DRAM (active-low).
VPP 64 P 5V power supply.
DRAS0# 67 O Row Address Strobe 0 to DRAM (active-low).
DWE# 68 O Write Enable to DRAM (active-low).
DOE# O Data Out Enable to DRAM (active-low).
MA9 O Multiplexed memory row and column address.
MA[8:0] 70:78 O Multiplexed memory row and column address.
59
60
69
Names Pin No. I/O Descriptions
DBUS[15:0] 79:94 I/O Input when DRAM is being read. Output when DRAM is being written.
REST# 96 I External system reset forces ES3890 to do a reset (active-low).
VSS_P 98 G Ground for system PLL.
VCC_P 99 P 2.5V power supply for system PLL.
AUX2[0] I/O General-purpose programmable I/O.
VFD_CLK I VFD clock
AUX2[1] I/O General-purpose programmable I/O.
SQSO I Subcode-Q data.
AUX2[2] I/O General-purpose programmable I/O.
SQCK I Subcode-Q clock.
AUX2[3] 103 I/O General-purpose programmable I/O.
AUX2[4] I/O General-purpose programmable I/O.
C2PO I C2PO error correction flag from CDROM.
AUX2[5] I/O General-purpose programmable I/O.
SP I Serial port from 16550 UART.
AUX2[6] I/O General-purpose programmable I/O.
S0S1 I Subcode-Q sync.
AUX2[7] 107 I/O General-purpose programmable I/O.
AUX1[5:0] 108:113 I/O General-purpose programmable I/O.
AUX1[6] I/O General-purpose programmable I/O.
VFD_DO O VFD data output.
AUX1[7] I/O General-purpose programmable I/O.
VFD_DI I VFD data input.
AUX0[1:0] 118,119 I/O General-purpose programmable I/O.
AUX0[2] 120 I General-purpose programmable input.
AUX0[3] 121 I/O General-purpose programmable I/O.
AUX0[4] 122 I/O General-purpose programmable input.
VSSV 123,124 G Ground for VDAC circuit.
VDAC 125 O Video DAC V output.
YDAC 126 O Video DAC Y output.
VCCV 127,128 P 2.5V power supply for video DAC circuit.
106
114
115
101
102
104
105
100
IC BLOCK DIAGRAM & DESCRIPTION
IC160 ES3890F (VCD Processor)
1
50
V
SS
V
CC
15 36
NC NC
NC
20 31
A8
32
NC
19
A9
21
30
A7A0
22
29
A6A1
23 28
A5A2
2724
A4A3
26
25
V
SS
V
CC
35
NC
16
LCAS
34
17
WE UCAS
3318
RAS OE
6 45
V
CC
V
SS
2 49
I/O1 I/O16
3 48
I/O2 I/O15
4 47
I/O3 I/O14
5 46
I/O4 I/O13
7
44
I/O5 I/O12
8 43
I/O6 I/O11
9 42
I/O7 I/O10
10 41
I/O8 I/O9
11
40
NC NC
PIN NO. PIN NAME TYPE DESCRIPTION
21-24, 27-32 A0-A9 Input
Address Input
Row Address : A0 - A9
Column Address : A0 - A9
18 RAS Input Row Address Strobe
34 UCAS Input Column Address Strobe / Upper Byte Control
35 LCAS Input Column Address Strobe / Lower Byte Control
17 WE Input Write Enable
33 OE Input Output Enable
2-5, 7-10, 41-44, 46-49 I/O1 - I/O16 Input / Output Data Input / Output
1, 6, 25 VCC Supply Power (3.3V)
26, 45, 50 VSS Ground Ground
11, 15, 16, 36, 40 NC - - - No Connect
IC190 M11L16161SA-45T (DRAM)
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