Sanyo dvw6100 - Mpeg Block Diagram

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4. MPEG BLOCK DIAGRAM
IC501
PANTERA-2
LE/PLUS
IC301
HC353106
IC305
SDRAM
16/32BIT
64M
IC502
93C46
EEPROM
IC3F1
FLASH
MEMORY
AD[0:7]
8
DSP I/F
DVD[0:7]
8
LA[0:3]
4
SCLK,SDATA
SQCK,SQS0
REQP
SDCLK1,PSYNC
DSP_INT
SENSE
/DSP_CS
AD[
04
:
21
]
RF & MOTOR I/F
MIRR
LDON
SCLK,S
DATA
EE_CS
F_IN
32
MD[00:31]
MCLK2
CKE
MA[00:10]
MA12,13
/CS0
/RAS/
/CAS
/WE
/DQM[0:3]
SPINDLE_FG
ALE
AD[04:19]
16
LADD[04:19]
16
LA[0:3]
4
AD[00:15]
16
AUDIO
DA_DATA[0:3} DA_BCK,DA_LRCK,DA_XCK
4
DAC_L0,DAC_L1
DAC_RST
TO VCR
C/R(B) CVBS/G(R) Y/B(G) CVBS
V_MUTE,16:9
ZISENB
/RD /PWED
IC301
DVW-6100
SANYO